diff options
| author | Anshuman Khandual <[email protected]> | 2023-06-14 12:29:47 +0530 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2023-06-14 14:37:34 +0100 |
| commit | 3077b1db9d5743c64343f47d88f1da89625c2590 (patch) | |
| tree | 5454f3ddd62c48bb22bc82092964935995349c83 | |
| parent | 46f3a5b01fd796f657ecbbefff9874e43e172391 (diff) | |
arm64/sysreg: Convert TRBMAR_EL1 register to automatic generation
This converts TRBMAR_EL1 register to automatic generation without
causing any functional change.
Cc: Will Deacon <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: James Morse <[email protected]>
Cc: [email protected]
Cc: [email protected]
Reviewed-by: Mark Brown <[email protected]>
Signed-off-by: Anshuman Khandual <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 5 | ||||
| -rw-r--r-- | arch/arm64/tools/sysreg | 16 |
2 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8382e46d1f3f..8d599f579c81 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -227,16 +227,11 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBMAR_EL1_SH_MASK GENMASK(9, 8) -#define TRBMAR_EL1_SH_SHIFT 8 -#define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) -#define TRBMAR_EL1_Attr_SHIFT 0 #define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) #define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_EL1_F BIT(5) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a8b1277318b1..8464d364cba1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2298,3 +2298,19 @@ Field 17 S Res0 16 Field 15:0 MSS EndSysreg + +Sysreg TRBMAR_EL1 3 0 9 11 4 +Res0 63:12 +Enum 11:10 PAS + 0b00 SECURE + 0b01 NON_SECURE + 0b10 ROOT + 0b11 REALM +EndEnum +Enum 9:8 SH + 0b00 NON_SHAREABLE + 0b10 OUTER_SHAREABLE + 0b11 INNER_SHAREABLE +EndEnum +Field 7:0 Attr +EndSysreg |