diff options
| author | Mark Brown <[email protected]> | 2024-02-13 15:32:45 +0000 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2024-02-22 19:39:34 +0000 |
| commit | 2f0090549b649cc9fd61c0193189c25f8fc03119 (patch) | |
| tree | bebec01eec42207b8e38167cc823b92fe856c464 | |
| parent | 21eb468e9fc11692952c42f86a44d07f94803d4f (diff) | |
arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values
At present nothing in our CPU initialisation code ever sets unknown fields
in ZCR_EL1 to known values, all updates to ZCR_EL1 are read/modify/write
sequences for LEN. All the unknown fields are RES0, explicitly initialise
them as such to avoid future surprises.
Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>
| -rw-r--r-- | arch/arm64/kernel/fpsimd.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index a5dc6f764195..cc3c9ad877a8 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1134,6 +1134,8 @@ void cpu_enable_sve(const struct arm64_cpu_capabilities *__always_unused p) { write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); isb(); + + write_sysreg_s(0, SYS_ZCR_EL1); } void __init sve_setup(void) |