diff options
| author | Mika Kuoppala <[email protected]> | 2019-10-15 18:44:46 +0300 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2019-10-15 18:23:10 +0100 |
| commit | 2e19af943822710cf00621eb32cc82394441bb60 (patch) | |
| tree | abda5bef22a51baea779c04ed589d34390949bf1 | |
| parent | 2cbe2d8c562eab58347b39342e37c7a2adbe7fef (diff) | |
drm/i915/tgl: Wa_1409600907
To avoid possible hang, we need to add depth stall if we flush the
depth cache.
Signed-off-by: Mika Kuoppala <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 62d5ece95c9d..d64b4d868b75 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3203,6 +3203,8 @@ static int gen12_emit_flush_render(struct i915_request *request, flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + /* Wa_1409600907:tgl */ + flags |= PIPE_CONTROL_DEPTH_STALL; flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; flags |= PIPE_CONTROL_FLUSH_ENABLE; flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; @@ -3435,6 +3437,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) PIPE_CONTROL_TILE_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | + /* Wa_1409600907:tgl */ + PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_DC_FLUSH_ENABLE | PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_HDC_PIPELINE_FLUSH); |