diff options
| author | Siddharth Vadapalli <[email protected]> | 2023-03-09 12:05:14 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2023-05-16 20:00:52 +0530 |
| commit | 2de2e49b3226cc6252c7dbf1a543e7546db416d3 (patch) | |
| tree | a3fa74d90d846cc88dac4c8ebb1e4810ef34b9b8 | |
| parent | 178b65152149628a59d9805c11b18527141a2b7b (diff) | |
phy: ti: gmii-sel: Enable SGMII mode for J721E
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
| -rw-r--r-- | drivers/phy/ti/phy-gmii-sel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index f3da6b020247..c87118cb2af9 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -230,7 +230,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), .num_ports = 8, .num_qsgmii_main_ports = 2, }; |