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authorOleksij Rempel <[email protected]>2023-01-31 09:46:33 +0100
committerShawn Guo <[email protected]>2023-03-06 10:01:46 +0800
commit2c23a919d655700f2b567ced1ed0307bfdede05e (patch)
tree303b77a477b66ea0836fe2d1acff8ca3573f4041
parent03c8a3c719884cb6a7e0f1cb328d58ee13d445d7 (diff)
ARM: dts: imx6dl-victgo: configure ethernet reference clock parent
On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
-rw-r--r--arch/arm/boot/dts/imx6dl-victgo.dts12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts
index 72df1dba83be..23274be08e61 100644
--- a/arch/arm/boot/dts/imx6dl-victgo.dts
+++ b/arch/arm/boot/dts/imx6dl-victgo.dts
@@ -54,6 +54,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
rotary-encoder {
@@ -134,6 +135,13 @@
};
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi2 {
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -182,10 +190,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rmii_phy>;
status = "okay";