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authorIcenowy Zheng <[email protected]>2020-02-22 00:51:27 +0800
committerThomas Zimmermann <[email protected]>2020-02-27 11:55:46 +0100
commit2be30d34a387b8d97cc1b4be1223bfe0b75a0812 (patch)
treef0c78479ddda30e143433d92222cc0b9e94a423b
parent8c8c06207bcfc5a7e5918fc0a0f7f7b9a2e196d6 (diff)
drm/bridge: analogix-anx6345: fix set of link bandwidth
Current code tries to store the link rate (in bps, which is a big number) in a u8, which surely overflow. Then it's converted back to bandwidth code (which is thus 0) and written to the chip. The code sometimes works because the chip will automatically fallback to the lowest possible DP link rate (1.62Gbps) when get the invalid value. However, on the eDP panel of Olimex TERES-I, which wants 2.7Gbps link, it failed. As we had already read the link bandwidth as bandwidth code in earlier code (to check whether it is supported), use it when setting bandwidth, instead of converting it to link rate and then converting back. Fixes: e1cff82c1097 ("drm/bridge: fix anx6345 compilation for v5.5") Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Torsten Duwe <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Torsten Duwe <[email protected]> Cc: Sam Ravnborg <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Thomas Zimmermann <[email protected]> Cc: Icenowy Zheng <[email protected]> Cc: Stephen Rothwell <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
-rw-r--r--drivers/gpu/drm/bridge/analogix/analogix-anx6345.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
index 56f55c53abfd..2dfa2fd2a23b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
@@ -210,8 +210,7 @@ static int anx6345_dp_link_training(struct anx6345 *anx6345)
if (err)
return err;
- dpcd[0] = drm_dp_max_link_rate(anx6345->dpcd);
- dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
+ dpcd[0] = dp_bw;
err = regmap_write(anx6345->map[I2C_IDX_DPTX],
SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
if (err)