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authorJoey Gouly <[email protected]>2023-06-06 15:58:45 +0100
committerCatalin Marinas <[email protected]>2023-06-06 16:52:40 +0100
commit2b760046a2d3d630d42bbe416f5d7f43792a1639 (patch)
tree553df27d2ba0ab6324b3f90761c3616b4fa7636b
parentedc25898f0b6cceed6c90b0e79916bd04de7dd19 (diff)
arm64: cpufeature: add TCR2 cpucap
This capability indicates if the system supports the TCR2_ELx system register. Signed-off-by: Joey Gouly <[email protected]> Cc: Will Deacon <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> Reviewed-by: Mark Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
-rw-r--r--arch/arm64/kernel/cpufeature.c6
-rw-r--r--arch/arm64/tools/cpucaps1
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 416c794207c1..12107c07fb77 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2674,6 +2674,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.cpu_enable = cpu_enable_mops,
ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
},
+ {
+ .capability = ARM64_HAS_TCR2,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_cpuid_feature,
+ ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
+ },
{},
};
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index debc4609f129..ebf5d4407b64 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -44,6 +44,7 @@ HAS_RAS_EXTN
HAS_RNG
HAS_SB
HAS_STAGE2_FWB
+HAS_TCR2
HAS_TIDCP1
HAS_TLB_RANGE
HAS_VIRT_HOST_EXTN