diff options
author | John Stultz <[email protected]> | 2021-03-30 01:34:08 +0000 |
---|---|---|
committer | Rob Clark <[email protected]> | 2021-04-01 14:19:16 -0700 |
commit | 2b0b219e5ff8bcc673d3a2cb6f327b3c62c5637d (patch) | |
tree | 5540961563456a46d0a318fcfe4fb46f15996711 | |
parent | 5620b135aea49a8f41c86aaecfcb1598a7774121 (diff) |
drm/msm: Fix removal of valid error case when checking speed_bin
Commit 7bf168c8fe8c ("drm/msm: Fix speed-bin support not to
access outside valid memory"), reworked the nvmem reading of
"speed_bin", but in doing so dropped handling of the -ENOENT
case which was previously documented as "fine".
That change resulted in the db845c board display to fail to
start, with the following error:
adreno 5000000.gpu: [drm:a6xx_gpu_init] *ERROR* failed to read speed-bin (-2). Some OPPs may not be supported by hardware
Thus, this patch simply re-adds the ENOENT handling so the lack
of the speed_bin entry isn't fatal for display, and gets things
working on db845c.
Cc: Rob Clark <[email protected]>
Cc: Sean Paul <[email protected]>
Cc: Jordan Crouse <[email protected]>
Cc: Eric Anholt <[email protected]>
Cc: Douglas Anderson <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Bjorn Andersson <[email protected]>
Cc: YongQin Liu <[email protected]>
Reported-by: YongQin Liu <[email protected]>
Fixes: 7bf168c8fe8c ("drm/msm: Fix speed-bin support not to access outside valid memory")
Signed-off-by: John Stultz <[email protected]>
Reviewed-by: Akhil P Oommen <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Rob Clark <[email protected]>
-rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 690409ca8a18..cb2df8736ca8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1406,7 +1406,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, int ret; ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin); - if (ret) { + /* + * -ENOENT means that the platform doesn't support speedbin which is + * fine + */ + if (ret == -ENOENT) { + return 0; + } else if (ret) { DRM_DEV_ERROR(dev, "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", ret); |