diff options
| author | Marc Zyngier <[email protected]> | 2023-08-15 19:38:41 +0100 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2023-08-17 10:00:26 +0100 |
| commit | 2b062ed483ebd625b6c6054b9d29d600bd755a86 (patch) | |
| tree | 0ea77e0762d5b9f22e1a36efcd85acd88366bfce | |
| parent | 57596c8f991c9aace47d75b31249b8ec36b3b899 (diff) | |
arm64: Add missing BRB/CFP/DVP/CPP instructions
HFGITR_EL2 traps a bunch of instructions for which we don't have
encodings yet. Add them.
Reviewed-by: Miguel Luis <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Reviewed-by: Jing Zhang <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index bb5a0877a210..6d9d7ac4b31c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -735,6 +735,13 @@ #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) +/* Misc instructions */ +#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) +#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) +#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) +#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) +#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) + /* Common SCTLR_ELx flags. */ #define SCTLR_ELx_ENTP2 (BIT(60)) #define SCTLR_ELx_DSSBS (BIT(44)) |