diff options
| author | Alex Bee <[email protected]> | 2021-05-28 16:07:36 +0200 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2021-05-28 17:53:19 +0200 |
| commit | 2adafc0512625bbd090dc37a353ddda15d525e9d (patch) | |
| tree | 8e418b45f2bfbb738bca4f59d4edbf2905b2db73 | |
| parent | 2f3877d609e7951ef96d24979eb9d163f1f004f8 (diff) | |
clk: rockchip: export ACLK_VCODEC for RK3036
It is required for the series at [1] to let hantro driver aquire the
clock and set the rate for RK3036 correctly, but I didn't want to
add a patch for yet another subsystem to this series.
[1] https://lore.kernel.org/linux-media/[email protected]/
Signed-off-by: Alex Bee <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3036.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 91d56ad45817..614845cc5b4a 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -259,7 +259,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKGATE_CON(1), 13, GFLAGS, &rk3036_uart2_fracmux), - COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, + COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0, RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 11, GFLAGS), FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4, |