diff options
| author | Geert Uytterhoeven <[email protected]> | 2022-02-21 17:25:20 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-04-13 12:27:45 +0200 |
| commit | 29db30c45f07c929c86c40a5b85f18b69c89c638 (patch) | |
| tree | 3da00d1cd8ce3cf20150f501dcdfa8b57e63dcbf | |
| parent | 9d18f81b35355f63a39b04869d0a013194925d1a (diff) | |
clk: renesas: rzg2l: Simplify multiplication/shift logic
"a * (1 << b)" == "a << b".
No change in generated code.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b3a1533970e5..f626d2704477 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) * (1 << SDIV(val2)); + div = PDIV(val1) << SDIV(val2); return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); } |