diff options
| author | Olof Johansson <[email protected]> | 2019-11-03 17:27:39 -0800 |
|---|---|---|
| committer | Olof Johansson <[email protected]> | 2019-11-03 17:27:40 -0800 |
| commit | 2687aa23f5d577ddc40bb575b12b19aab656b405 (patch) | |
| tree | 2d6e5d4f5bde1a5634537461612ce9a24794e33e | |
| parent | c267d9960cc5f447ddc8863ed13af5b7d12d2f06 (diff) | |
| parent | 4053aa65c517fba954af05e826bb97b2eaefe92a (diff) | |
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.5-rc1
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
* tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
ARM: tegra: trimslice: Add CPU Operating Performance Points
ARM: tegra: paz00: Add CPU Operating Performance Points
ARM: tegra: paz00: Set up voltage regulators for DVFS
ARM: tegra: Add CPU Operating Performance Points for Tegra30
ARM: tegra: Add CPU Operating Performance Points for Tegra20
ARM: tegra: Add Tegra30 CPU clock
ARM: tegra: Add Tegra20 CPU clock
ARM: tegra: Add External Memory Controller node on Tegra30
ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
ARM: tegra: Add eDP power supplies on Venice2
ARM: tegra: Add SOR0_OUT clock on Tegra124
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Olof Johansson <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 7869 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra124-venice2.dts | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi | 201 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 302 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra20-paz00.dts | 41 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 11 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 22 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-apalis.dtsi | 22 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu-a04.dts | 48 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-colibri.dtsi | 22 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi | 801 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 1202 | ||||
| -rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 14 |
15 files changed, 8910 insertions, 1653 deletions
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 9af21fe93a5c..fb6b3e1a0b1f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 / { + apbmisc@70000800 { + nvidia,long-ram-code; + }; + clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -52,7 +56,154 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_M>; clock-names = "emc-parent"; }; - /* TODO: Add 528MHz frequency */ + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + timing-600000000 { + clock-frequency = <600000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; + clock-names = "emc-parent"; + }; + timing-792000000 { + clock-frequency = <792000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-20400000 { + clock-frequency = <20400000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-40800000 { + clock-frequency = <40800000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-68000000 { + clock-frequency = <68000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,parent-clock-frequency = <408000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "emc-parent"; + }; + timing-300000000 { + clock-frequency = <300000000>; + nvidia,parent-clock-frequency = <600000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_C>; + clock-names = "emc-parent"; + }; + timing-396000000 { + clock-frequency = <396000000>; + nvidia,parent-clock-frequency = <792000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M>; + clock-names = "emc-parent"; + }; + timing-528000000 { + clock-frequency = <528000000>; + nvidia,parent-clock-frequency = <528000000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; + clock-names = "emc-parent"; + }; timing-600000000 { clock-frequency = <600000000>; nvidia,parent-clock-frequency = <600000000>; @@ -94,149 +245,149 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000060 - 0x00000000 - 0x00000018 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000005 - 0x00000005 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000064 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000007 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x800001c5 - 0x0000000a + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -262,149 +413,149 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000000 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x0000009a - 0x00000000 - 0x00000026 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000007 - 0x0000000f - 0x00000006 - 0x00000006 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x000000a0 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x0000000b - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000023a - 0x0000000a + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -430,149 +581,149 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000001 - 0x0000000a - 0x00000000 - 0x00000001 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000134 - 0x00000000 - 0x0000004d - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000008 - 0x0000000f - 0x0000000c - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000013f - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000015 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000370 - 0x0000000a + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -598,149 +749,149 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000003 - 0x00000011 - 0x00000000 - 0x00000002 - 0x00000000 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000000 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000202 - 0x00000000 - 0x00000080 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x0000000f - 0x0000000f - 0x00000013 - 0x00000013 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000001 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000213 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000022 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x8000050e - 0x0000000a + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -766,149 +917,149 @@ nvidia,emc-zcal-interval = <0x00000000>; nvidia,emc-configuration = < - 0x00000004 - 0x0000001a - 0x00000000 - 0x00000003 - 0x00000001 - 0x00000004 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x0000000c - 0x0000000d - 0x0000000f - 0x00000304 - 0x00000000 - 0x000000c1 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000018 - 0x0000000f - 0x0000001c - 0x0000001c - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000031c - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x000fc000 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x0000fc00 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000033 - 0x00000000 - 0x00000042 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000f2f3 - 0x80000713 - 0x0000000a + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -934,149 +1085,149 @@ nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000009 - 0x00000035 - 0x00000000 - 0x00000007 - 0x00000002 - 0x00000005 - 0x0000000a - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000003 - 0x00000003 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000006 - 0x00000002 - 0x00000000 - 0x00000004 - 0x00000006 - 0x00010000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000003 - 0x0000000d - 0x0000000f - 0x00000011 - 0x00000607 - 0x00000000 - 0x00000181 - 0x00000002 - 0x00000002 - 0x00000001 - 0x00000000 - 0x00000032 - 0x0000000f - 0x00000038 - 0x00000038 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000007 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000638 - 0x00000000 - 0x00000000 - 0x00000000 - 0x106aa298 - 0x002c00a0 - 0x00008000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00064000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00004000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00090000 - 0x00090000 - 0x00094000 - 0x00094000 - 0x00009400 - 0x00009000 - 0x00009000 - 0x00009000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000303 - 0x81f1f108 - 0x07070004 - 0x0000003f - 0x016eeeee - 0x51451400 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000066 - 0x00000000 - 0x00000100 - 0x000c000c - 0x00000000 - 0x00000003 - 0x0000d2b3 - 0x80000d22 - 0x0000000a + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ >; }; @@ -1102,149 +1253,149 @@ nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000000d - 0x0000004c - 0x00000000 - 0x00000009 - 0x00000003 - 0x00000004 - 0x00000008 - 0x00000002 - 0x00000009 - 0x00000003 - 0x00000003 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000007 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x0000000e - 0x00000010 - 0x00000012 - 0x000008e4 - 0x00000000 - 0x00000239 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x0000004a - 0x0000000e - 0x00000051 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000009 - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000924 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00098000 - 0x00098000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00060000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x00006000 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x00000096 - 0x00000000 - 0x00000100 - 0x0174000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x800012d7 - 0x00000009 + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ >; }; @@ -1270,149 +1421,317 @@ nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000012 - 0x00000065 - 0x00000000 - 0x0000000c - 0x00000004 - 0x00000005 - 0x00000008 - 0x00000002 - 0x0000000a - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000003 - 0x00000003 - 0x00000005 - 0x00000002 - 0x00000000 - 0x00000001 - 0x00000008 - 0x00020000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x0000000f - 0x00000010 - 0x00000012 - 0x00000bd1 - 0x00000000 - 0x000002f4 - 0x00000001 - 0x00000008 - 0x00000001 - 0x00000000 - 0x00000063 - 0x0000000f - 0x0000006b - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x0000000d - 0x00000000 - 0x00000005 - 0x00000005 - 0x00000c11 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0x002c00a0 - 0x00008000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00030000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00070000 - 0x00070000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00048000 - 0x00048000 - 0x00004800 - 0x00004800 - 0x00004800 - 0x00004800 - 0x10000280 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc081 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0000003f - 0x000000c6 - 0x00000000 - 0x00000100 - 0x015b000c - 0x00000000 - 0x00000003 - 0x000052a3 - 0x8000188b - 0x00000009 + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ >; }; @@ -1438,149 +1757,149 @@ nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x0000001c - 0x0000009a - 0x00000000 - 0x00000013 - 0x00000007 - 0x00000007 - 0x0000000b - 0x00000003 - 0x00000010 - 0x00000007 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000000 - 0x00000005 - 0x00000005 - 0x0000000a - 0x00000002 - 0x00000000 - 0x00000003 - 0x0000000b - 0x00070000 - 0x00000003 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000002 - 0x00000012 - 0x00000016 - 0x00000018 - 0x00001208 - 0x00000000 - 0x00000482 - 0x00000002 - 0x0000000d - 0x00000001 - 0x00000000 - 0x00000096 - 0x00000015 - 0x000000a2 - 0x00000200 - 0x00000004 - 0x00000005 - 0x00000004 - 0x00000015 - 0x00000000 - 0x00000006 - 0x00000006 - 0x00001249 - 0x00000000 - 0x00000000 - 0x00000000 - 0x104ab098 - 0xe00e00b1 - 0x00008000 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00048000 - 0x00048000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000005 - 0x00000006 - 0x00000003 - 0x00000006 - 0x00000005 - 0x00000004 - 0x00000004 - 0x00000002 - 0x00000005 - 0x00000006 - 0x00000003 - 0x00000006 - 0x00000005 - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x0000000e - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x51451420 - 0x00514514 - 0x00514514 - 0x51451400 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x0128000c - 0x00000000 - 0x00000003 - 0x000040a0 - 0x800024aa - 0x0000000e + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; @@ -1606,152 +1925,3855 @@ nvidia,emc-zcal-interval = <0x00020000>; nvidia,emc-configuration = < - 0x00000025 - 0x000000cc - 0x00000000 - 0x0000001a - 0x00000009 - 0x00000008 - 0x0000000d - 0x00000004 - 0x00000013 - 0x00000009 - 0x00000009 - 0x00000003 - 0x00000002 - 0x00000000 - 0x00000006 - 0x00000006 - 0x0000000b - 0x00000002 - 0x00000000 - 0x00000002 - 0x0000000d - 0x00080000 - 0x00000004 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000001 - 0x00000014 - 0x00000018 - 0x0000001a - 0x000017e2 - 0x00000000 - 0x000005f8 - 0x00000003 - 0x00000011 - 0x00000001 - 0x00000000 - 0x000000c6 - 0x00000018 - 0x000000d6 - 0x00000200 - 0x00000005 - 0x00000006 - 0x00000005 - 0x0000001d - 0x00000000 - 0x00000008 - 0x00000008 - 0x00001822 - 0x00000000 - 0x80000005 - 0x00000000 - 0x104ab198 - 0xe00700b1 - 0x00008000 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000005 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00034000 - 0x00034000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000009 - 0x00000009 - 0x00000007 - 0x00000009 - 0x00000008 - 0x00000008 - 0x00000008 - 0x00000005 - 0x00000009 - 0x00000009 - 0x00000007 - 0x00000009 - 0x00000008 - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x0000000a - 0x100002a0 - 0x00000000 - 0x00111111 - 0x00000000 - 0x00000000 - 0x77ffc085 - 0x00000101 - 0x81f1f108 - 0x07070004 - 0x00000000 - 0x016eeeee - 0x61861820 - 0x00514514 - 0x00514514 - 0x61861800 - 0x0606003f - 0x00000000 - 0x00000000 - 0x00000100 - 0x00f8000c - 0x00000007 - 0x00000004 - 0x00004080 - 0x80003012 - 0x0000000f + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000005 /* EMC_DLL_XFORM_DQS0 */ + 0x00000005 /* EMC_DLL_XFORM_DQS1 */ + 0x00000005 /* EMC_DLL_XFORM_DQS2 */ + 0x00000005 /* EMC_DLL_XFORM_DQS3 */ + 0x00000005 /* EMC_DLL_XFORM_DQS4 */ + 0x00000005 /* EMC_DLL_XFORM_DQS5 */ + 0x00000005 /* EMC_DLL_XFORM_DQS6 */ + 0x00000005 /* EMC_DLL_XFORM_DQS7 */ + 0x00000005 /* EMC_DLL_XFORM_DQS8 */ + 0x00000005 /* EMC_DLL_XFORM_DQS9 */ + 0x00000005 /* EMC_DLL_XFORM_DQS10 */ + 0x00000005 /* EMC_DLL_XFORM_DQS11 */ + 0x00000005 /* EMC_DLL_XFORM_DQS12 */ + 0x00000005 /* EMC_DLL_XFORM_DQS13 */ + 0x00000005 /* EMC_DLL_XFORM_DQS14 */ + 0x00000005 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a /* EMC_DLL_XFORM_DQ4 */ + 0x0000000a /* EMC_DLL_XFORM_DQ5 */ + 0x0000000a /* EMC_DLL_XFORM_DQ6 */ + 0x0000000a /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000004 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000e /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000f /* EMC_TXSR */ + 0x0000000f /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000017 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000015 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000019 /* EMC_TXSR */ + 0x00000019 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x00000023 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000021 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000025 /* EMC_TXSR */ + 0x00000025 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x00008000 /* EMC_DLL_XFORM_DQ4 */ + 0x00008000 /* EMC_DLL_XFORM_DQ5 */ + 0x00008000 /* EMC_DLL_XFORM_DQ6 */ + 0x00008000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100003>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00001221>; + nvidia,emc-mrs-wait-cnt = <0x000e000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000047 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000006 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000044 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000004a /* EMC_TXSR */ + 0x0000004a /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000e000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000321>; + nvidia,emc-mrs-wait-cnt = <0x0117000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x00000067 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000065 /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0117000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000521>; + nvidia,emc-mrs-wait-cnt = <0x00f5000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000011 /* EMC_RC */ + 0x00000089 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000087 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f5000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000941>; + nvidia,emc-mrs-wait-cnt = <0x00c8000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x000000b7 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000010 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000b4 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x000000bf /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00c8000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000b61>; + nvidia,emc-mrs-wait-cnt = <0x00b0000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001b /* EMC_RC */ + 0x000000d0 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000cc /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00b0000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x00100002>; + nvidia,emc-mode-2 = <0x00200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x00000d71>; + nvidia,emc-mrs-wait-cnt = <0x006f000e>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000024 /* EMC_RC */ + 0x00000114 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000019 /* EMC_RAS */ + 0x0000000a /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x0000000a /* EMC_RD_RCD */ + 0x0000000a /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000010d /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x0000011e /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x007fc007 /* EMC_DLL_XFORM_DQS0 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS1 */ + 0x007f400c /* EMC_DLL_XFORM_DQS2 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS3 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS4 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS5 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS6 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS7 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS8 */ + 0x007fc008 /* EMC_DLL_XFORM_DQS9 */ + 0x007f400c /* EMC_DLL_XFORM_DQS10 */ + 0x007fc007 /* EMC_DLL_XFORM_DQS11 */ + 0x007f4006 /* EMC_DLL_XFORM_DQS12 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS13 */ + 0x007f8005 /* EMC_DLL_XFORM_DQS14 */ + 0x007f8004 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x00492492 /* EMC_XM2DQSPADCTRL4 */ + 0x00492492 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x006f000e /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000003 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000060 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000005 /* EMC_TXSR */ + 0x00000005 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000064 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000007 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000000 /* EMC_RC */ + 0x00000005 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x0000009a /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000006 /* EMC_TXSR */ + 0x00000006 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000a0 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x0000000b /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x0000000a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000134 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000c /* EMC_TXSR */ + 0x0000000c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000000 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000013f /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000015 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000003 /* EMC_RC */ + 0x00000011 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000002 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000202 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000013 /* EMC_TXSR */ + 0x00000013 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000001 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000213 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000022 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x000008c5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00000000>; + + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000005 /* EMC_EINPUT */ + 0x00000005 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000004 /* EMC_QRST */ + 0x0000000c /* EMC_QSAFE */ + 0x0000000d /* EMC_RDV */ + 0x0000000f /* EMC_RDV_MASK */ + 0x00000304 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000018 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ + 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000033 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000042 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000f2f3 /* EMC_CFG_PIPE */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000008>; + nvidia,emc-cfg = <0x73240000>; + nvidia,emc-cfg-2 = <0x0000088d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-mrs-wait-cnt = <0x000c000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000003 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x00000006 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000004 /* EMC_EINPUT */ + 0x00000006 /* EMC_EINPUT_DURATION */ + 0x00010000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000003 /* EMC_QRST */ + 0x0000000d /* EMC_QSAFE */ + 0x0000000f /* EMC_RDV */ + 0x00000011 /* EMC_RDV_MASK */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000032 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000007 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x106aa298 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000 /* EMC_DLL_XFORM_DQS0 */ + 0x00064000 /* EMC_DLL_XFORM_DQS1 */ + 0x00064000 /* EMC_DLL_XFORM_DQS2 */ + 0x00064000 /* EMC_DLL_XFORM_DQS3 */ + 0x00064000 /* EMC_DLL_XFORM_DQS4 */ + 0x00064000 /* EMC_DLL_XFORM_DQS5 */ + 0x00064000 /* EMC_DLL_XFORM_DQS6 */ + 0x00064000 /* EMC_DLL_XFORM_DQS7 */ + 0x00064000 /* EMC_DLL_XFORM_DQS8 */ + 0x00064000 /* EMC_DLL_XFORM_DQS9 */ + 0x00064000 /* EMC_DLL_XFORM_DQS10 */ + 0x00064000 /* EMC_DLL_XFORM_DQS11 */ + 0x00064000 /* EMC_DLL_XFORM_DQS12 */ + 0x00064000 /* EMC_DLL_XFORM_DQS13 */ + 0x00064000 /* EMC_DLL_XFORM_DQS14 */ + 0x00064000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00004000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00090000 /* EMC_DLL_XFORM_DQ0 */ + 0x00090000 /* EMC_DLL_XFORM_DQ1 */ + 0x00094000 /* EMC_DLL_XFORM_DQ2 */ + 0x00094000 /* EMC_DLL_XFORM_DQ3 */ + 0x00009400 /* EMC_DLL_XFORM_DQ4 */ + 0x00009000 /* EMC_DLL_XFORM_DQ5 */ + 0x00009000 /* EMC_DLL_XFORM_DQ6 */ + 0x00009000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000303 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451400 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000066 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x0000d2b3 /* EMC_CFG_PIPE */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000a /* EMC_QPOP */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x000008d5>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-mrs-wait-cnt = <0x0174000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040128>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000000d /* EMC_RC */ + 0x0000004c /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000009 /* EMC_RAS */ + 0x00000003 /* EMC_RP */ + 0x00000004 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x00000009 /* EMC_W2P */ + 0x00000003 /* EMC_RD_RCD */ + 0x00000003 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000007 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x0000000e /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x000008e4 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000004a /* EMC_AR2PDEN */ + 0x0000000e /* EMC_RW2PDEN */ + 0x00000051 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000924 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00098000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00060000 /* EMC_DLL_XFORM_DQ0 */ + 0x00060000 /* EMC_DLL_XFORM_DQ1 */ + 0x00060000 /* EMC_DLL_XFORM_DQ2 */ + 0x00060000 /* EMC_DLL_XFORM_DQ3 */ + 0x00006000 /* EMC_DLL_XFORM_DQ4 */ + 0x00006000 /* EMC_DLL_XFORM_DQ5 */ + 0x00006000 /* EMC_DLL_XFORM_DQ6 */ + 0x00006000 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000096 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0174000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73340000>; + nvidia,emc-cfg-2 = <0x00000895>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-mrs-wait-cnt = <0x015b000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x01231339>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000065 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000005 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000001 /* EMC_EINPUT */ + 0x00000008 /* EMC_EINPUT_DURATION */ + 0x00020000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000000 /* EMC_QRST */ + 0x0000000f /* EMC_QSAFE */ + 0x00000010 /* EMC_RDV */ + 0x00000012 /* EMC_RDV_MASK */ + 0x00000bd1 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000063 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006b /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x0000000d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000005 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c11 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0x002c00a0 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00030000 /* EMC_DLL_XFORM_DQS0 */ + 0x00030000 /* EMC_DLL_XFORM_DQS1 */ + 0x00030000 /* EMC_DLL_XFORM_DQS2 */ + 0x00030000 /* EMC_DLL_XFORM_DQS3 */ + 0x00030000 /* EMC_DLL_XFORM_DQS4 */ + 0x00030000 /* EMC_DLL_XFORM_DQS5 */ + 0x00030000 /* EMC_DLL_XFORM_DQS6 */ + 0x00030000 /* EMC_DLL_XFORM_DQS7 */ + 0x00030000 /* EMC_DLL_XFORM_DQS8 */ + 0x00030000 /* EMC_DLL_XFORM_DQS9 */ + 0x00030000 /* EMC_DLL_XFORM_DQS10 */ + 0x00030000 /* EMC_DLL_XFORM_DQS11 */ + 0x00030000 /* EMC_DLL_XFORM_DQS12 */ + 0x00030000 /* EMC_DLL_XFORM_DQS13 */ + 0x00030000 /* EMC_DLL_XFORM_DQS14 */ + 0x00030000 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00070000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x00004800 /* EMC_DLL_XFORM_DQ4 */ + 0x00004800 /* EMC_DLL_XFORM_DQ5 */ + 0x00004800 /* EMC_DLL_XFORM_DQ6 */ + 0x00004800 /* EMC_DLL_XFORM_DQ7 */ + 0x10000280 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc081 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0000003f /* EMC_DSR_VTTGEN_DRV */ + 0x000000c6 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x015b000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000052a3 /* EMC_CFG_PIPE */ + 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000009 /* EMC_QPOP */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000941>; + nvidia,emc-mrs-wait-cnt = <0x013a000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0123133d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000018 /* EMC_RC */ + 0x00000088 /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000011 /* EMC_RAS */ + 0x00000006 /* EMC_RP */ + 0x00000006 /* EMC_R2W */ + 0x00000009 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000d /* EMC_W2P */ + 0x00000006 /* EMC_RD_RCD */ + 0x00000006 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000003 /* EMC_WDV */ + 0x00000003 /* EMC_WDV_MASK */ + 0x00000007 /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x00000009 /* EMC_EINPUT_DURATION */ + 0x00040000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000010 /* EMC_QSAFE */ + 0x00000013 /* EMC_RDV */ + 0x00000015 /* EMC_RDV_MASK */ + 0x00000fd6 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000b /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000084 /* EMC_AR2PDEN */ + 0x00000012 /* EMC_RW2PDEN */ + 0x0000008f /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000013 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001017 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe01200b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00050000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x013a000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000042a0 /* EMC_CFG_PIPE */ + 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b /* EMC_QPOP */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0000089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200010>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000b61>; + nvidia,emc-mrs-wait-cnt = <0x0128000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040008>; + nvidia,emc-xm2dqspadctrl2 = <0x0121113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x0000001c /* EMC_RC */ + 0x0000009a /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x00000013 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000007 /* EMC_R2W */ + 0x0000000b /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000010 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_WDV_MASK */ + 0x0000000a /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000003 /* EMC_EINPUT */ + 0x0000000b /* EMC_EINPUT_DURATION */ + 0x00070000 /* EMC_PUTERM_EXTRA */ + 0x00000003 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000002 /* EMC_QRST */ + 0x00000012 /* EMC_QSAFE */ + 0x00000016 /* EMC_RDV */ + 0x00000018 /* EMC_RDV_MASK */ + 0x00001208 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000d /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000096 /* EMC_AR2PDEN */ + 0x00000015 /* EMC_RW2PDEN */ + 0x000000a2 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TCKESR */ + 0x00000004 /* EMC_TPD */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000006 /* EMC_TCLKSTOP */ + 0x00001249 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab098 /* EMC_FBIO_CFG5 */ + 0xe00e00b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQS8 */ + 0x0000000a /* EMC_DLL_XFORM_DQS9 */ + 0x0000000a /* EMC_DLL_XFORM_DQS10 */ + 0x0000000a /* EMC_DLL_XFORM_DQS11 */ + 0x0000000a /* EMC_DLL_XFORM_DQS12 */ + 0x0000000a /* EMC_DLL_XFORM_DQS13 */ + 0x0000000a /* EMC_DLL_XFORM_DQS14 */ + 0x0000000a /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR0 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR3 */ + 0x00048000 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x51451420 /* EMC_XM2DQSPADCTRL3 */ + 0x00514514 /* EMC_XM2DQSPADCTRL4 */ + 0x00514514 /* EMC_XM2DQSPADCTRL5 */ + 0x51451400 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000000 /* EMC_CTT */ + 0x00000003 /* EMC_CTT_DURATION */ + 0x000040a0 /* EMC_CFG_PIPE */ + 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000e /* EMC_QPOP */ >; }; + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emc-auto-cal-config = <0xa1430000>; + nvidia,emc-auto-cal-config2 = <0x00000000>; + nvidia,emc-auto-cal-config3 = <0x00000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-bgbias-ctl0 = <0x00000000>; + nvidia,emc-cfg = <0x73300000>; + nvidia,emc-cfg-2 = <0x0080089d>; + nvidia,emc-ctt-term-ctrl = <0x00000802>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200418>; + nvidia,emc-mode-4 = <0x00000000>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-mrs-wait-cnt = <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl = <0x00040000>; + nvidia,emc-xm2dqspadctrl2 = <0x0120113d>; + nvidia,emc-zcal-cnt-long = <0x00000042>; + nvidia,emc-zcal-interval = <0x00020000>; + + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000cc /* EMC_RFC */ + 0x00000000 /* EMC_RFC_SLR */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000008 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000002 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000006 /* EMC_WDV */ + 0x00000006 /* EMC_WDV_MASK */ + 0x0000000b /* EMC_QUSE */ + 0x00000002 /* EMC_QUSE_WIDTH */ + 0x00000000 /* EMC_IBDLY */ + 0x00000002 /* EMC_EINPUT */ + 0x0000000d /* EMC_EINPUT_DURATION */ + 0x00080000 /* EMC_PUTERM_EXTRA */ + 0x00000004 /* EMC_PUTERM_WIDTH */ + 0x00000000 /* EMC_PUTERM_ADJ */ + 0x00000000 /* EMC_CDB_CNTL_1 */ + 0x00000000 /* EMC_CDB_CNTL_2 */ + 0x00000000 /* EMC_CDB_CNTL_3 */ + 0x00000001 /* EMC_QRST */ + 0x00000014 /* EMC_QSAFE */ + 0x00000018 /* EMC_RDV */ + 0x0000001a /* EMC_RDV_MASK */ + 0x000017e2 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000011 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x000000c6 /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d6 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000006 /* EMC_TCKESR */ + 0x00000005 /* EMC_TPD */ + 0x0000001d /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000008 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001822 /* EMC_TREFBW */ + 0x00000000 /* EMC_FBIO_CFG6 */ + 0x80000005 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x104ab198 /* EMC_FBIO_CFG5 */ + 0xe00700b1 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000009 /* EMC_DLL_XFORM_DQS0 */ + 0x00000009 /* EMC_DLL_XFORM_DQS1 */ + 0x00000009 /* EMC_DLL_XFORM_DQS2 */ + 0x00000007 /* EMC_DLL_XFORM_DQS3 */ + 0x00000006 /* EMC_DLL_XFORM_DQS4 */ + 0x00000006 /* EMC_DLL_XFORM_DQS5 */ + 0x007fc009 /* EMC_DLL_XFORM_DQS6 */ + 0x00000006 /* EMC_DLL_XFORM_DQS7 */ + 0x00000009 /* EMC_DLL_XFORM_DQS8 */ + 0x00000009 /* EMC_DLL_XFORM_DQS9 */ + 0x00000009 /* EMC_DLL_XFORM_DQS10 */ + 0x00000007 /* EMC_DLL_XFORM_DQS11 */ + 0x00000006 /* EMC_DLL_XFORM_DQS12 */ + 0x00000007 /* EMC_DLL_XFORM_DQS13 */ + 0x00000009 /* EMC_DLL_XFORM_DQS14 */ + 0x00000007 /* EMC_DLL_XFORM_DQS15 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR0 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR3 */ + 0x00034002 /* EMC_DLL_XFORM_ADDR4 */ + 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */ + 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */ + 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */ + 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */ + 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */ + 0x0000000e /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e /* EMC_DLL_XFORM_DQ1 */ + 0x0000000e /* EMC_DLL_XFORM_DQ2 */ + 0x0000000e /* EMC_DLL_XFORM_DQ3 */ + 0x0000000e /* EMC_DLL_XFORM_DQ4 */ + 0x0000000e /* EMC_DLL_XFORM_DQ5 */ + 0x0000000e /* EMC_DLL_XFORM_DQ6 */ + 0x0000000e /* EMC_DLL_XFORM_DQ7 */ + 0x100002a0 /* EMC_XM2CMDPADCTRL */ + 0x00000000 /* EMC_XM2CMDPADCTRL4 */ + 0x00111111 /* EMC_XM2CMDPADCTRL5 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL3 */ + 0x77ffc085 /* EMC_XM2CLKPADCTRL */ + 0x00000101 /* EMC_XM2CLKPADCTRL2 */ + 0x81f1f108 /* EMC_XM2COMPPADCTRL */ + 0x07070004 /* EMC_XM2VTTGENPADCTRL */ + 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ + 0x61861820 /* EMC_XM2DQSPADCTRL3 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */ + 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */ + 0x61861800 /* EMC_XM2DQSPADCTRL6 */ + 0x0606003f /* EMC_DSR_VTTGEN_DRV */ + 0x00000000 /* EMC_TXDSRVTTGEN */ + 0x00000000 /* EMC_FBIO_SPARE */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000c /* EMC_MRS_WAIT_CNT2 */ + 0x00000007 /* EMC_CTT */ + 0x00000004 /* EMC_CTT_DURATION */ + 0x00004080 /* EMC_CFG_PIPE */ + 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f /* EMC_QPOP */ + >; + }; }; }; @@ -1759,30 +5781,609 @@ emc-timings-1 { nvidia,ram-code = <1>; + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-4 { + nvidia,ram-code = <4>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-20400000 { + clock-frequency = <20400000>; + + nvidia,emem-configuration = < + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x77430303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-40800000 { + clock-frequency = <40800000>; + + nvidia,emem-configuration = < + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-68000000 { + clock-frequency = <68000000>; + + nvidia,emem-configuration = < + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75430403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a40a05 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-300000000 { + clock-frequency = <300000000>; + + nvidia,emem-configuration = < + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-396000000 { + clock-frequency = <396000000>; + + nvidia,emem-configuration = < + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c /* MC_EMEM_ARB_DA_COVERS */ + 0x7488180d /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-600000000 { + clock-frequency = <600000000>; + + nvidia,emem-configuration = < + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x74691b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-792000000 { + clock-frequency = <792000000>; + + nvidia,emem-configuration = < + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */ + 0x746c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + + emc-timings-6 { + nvidia,ram-code = <6>; timing-12750000 { clock-frequency = <12750000>; nvidia,emem-configuration = < - 0x40040001 - 0x8000000a - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x77e30303 - 0x70000f03 - 0x001f0000 + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1790,25 +6391,25 @@ clock-frequency = <20400000>; nvidia,emem-configuration = < - 0x40020001 - 0x80000012 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x76230303 - 0x70000f03 - 0x001f0000 + 0x40020001 /* MC_EMEM_ARB_CFG */ + 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1816,25 +6417,25 @@ clock-frequency = <40800000>; nvidia,emem-configuration = < - 0xa0000001 - 0x80000017 - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74a30303 - 0x70000f03 - 0x001f0000 + 0xa0000001 /* MC_EMEM_ARB_CFG */ + 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1842,25 +6443,25 @@ clock-frequency = <68000000>; nvidia,emem-configuration = < - 0x00000001 - 0x8000001e - 0x00000001 - 0x00000001 - 0x00000002 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0402 - 0x74230403 - 0x70000f03 - 0x001f0000 + 0x00000001 /* MC_EMEM_ARB_CFG */ + 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1868,25 +6469,25 @@ clock-frequency = <102000000>; nvidia,emem-configuration = < - 0x08000001 - 0x80000026 - 0x00000001 - 0x00000001 - 0x00000003 - 0x00000000 - 0x00000002 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000003 - 0x00000006 - 0x06030203 - 0x000a0403 - 0x73c30504 - 0x70000f03 - 0x001f0000 + 0x08000001 /* MC_EMEM_ARB_CFG */ + 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1894,25 +6495,25 @@ clock-frequency = <204000000>; nvidia,emem-configuration = < - 0x01000003 - 0x80000040 - 0x00000001 - 0x00000001 - 0x00000005 - 0x00000002 - 0x00000004 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000003 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040203 - 0x000a0405 - 0x73840a06 - 0x70000f03 - 0x001f0000 + 0x01000003 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1920,25 +6521,25 @@ clock-frequency = <300000000>; nvidia,emem-configuration = < - 0x08000004 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000004 - 0x00000005 - 0x00000001 - 0x00000002 - 0x00000007 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000b0607 - 0x77450e08 - 0x70000f03 - 0x001f0000 + 0x08000004 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */ + 0x77450e08 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1946,25 +6547,51 @@ clock-frequency = <396000000>; nvidia,emem-configuration = < - 0x0f000005 - 0x80000040 - 0x00000001 - 0x00000002 - 0x00000009 - 0x00000005 - 0x00000007 - 0x00000001 - 0x00000002 - 0x00000008 - 0x00000002 - 0x00000002 - 0x00000004 - 0x00000006 - 0x06040202 - 0x000d0709 - 0x7586120a - 0x70000f03 - 0x001f0000 + 0x0f000005 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7586120a /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + + timing-528000000 { + clock-frequency = <528000000>; + + nvidia,emem-configuration = < + 0x0f000007 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180e /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1972,25 +6599,25 @@ clock-frequency = <600000000>; nvidia,emem-configuration = < - 0x00000009 - 0x80000040 - 0x00000003 - 0x00000004 - 0x0000000e - 0x00000009 - 0x0000000b - 0x00000001 - 0x00000003 - 0x0000000b - 0x00000002 - 0x00000002 - 0x00000005 - 0x00000007 - 0x07050202 - 0x00130b0e - 0x73a91b0f - 0x70000f03 - 0x001f0000 + 0x00000009 /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000e /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */ + 0x73a91b0f /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; @@ -1998,25 +6625,25 @@ clock-frequency = <792000000>; nvidia,emem-configuration = < - 0x0e00000b - 0x80000040 - 0x00000004 - 0x00000005 - 0x00000013 - 0x0000000c - 0x0000000f - 0x00000002 - 0x00000003 - 0x0000000c - 0x00000002 - 0x00000002 - 0x00000006 - 0x00000008 - 0x08060202 - 0x00160d13 - 0x734c2414 - 0x70000f02 - 0x001f0000 + 0x0e00000b /* MC_EMEM_ARB_CFG */ + 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414 /* MC_EMEM_ARB_MISC0 */ + 0x70000f02 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ >; }; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 5d5e6e18bc7b..7309393bfced 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -38,6 +38,9 @@ sor@54540000 { status = "okay"; + avdd-io-hdmi-dp-supply = <&vdd_1v05_run>; + vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>; + nvidia,dpaux = <&dpaux>; nvidia,panel = <&panel>; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b113e47b2b2a..413bfb981de8 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -157,10 +157,11 @@ reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_SOR0_OUT>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi new file mode 100644 index 000000000000..e85ffdbef876 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + opp@216000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@216000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@312000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@312000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@456000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_800_2_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_800_3_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp@608000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@608000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@608000000_800_3_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@608000000_825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp@608000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@608000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@760000000_775 { + opp-microvolt = <775000 775000 1125000>; + }; + + opp@760000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@760000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@760000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_1_1 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_0_2 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_1_2 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@760000000_975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp@816000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@816000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@816000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@816000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@816000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@912000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@912000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@912000000_925 { + opp-microvolt = <925000 925000 1125000>; + }; + + opp@912000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_950_0_2 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_950_2_2 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@912000000_1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp@1000000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@1000000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@1000000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@1000000000_975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp@1000000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1000000000_1000_0_2 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1000000000_1025 { + opp-microvolt = <1025000 1025000 1125000>; + }; + + opp@1000000000_1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp@1200000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1200000000_1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp@1200000000_1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp@1200000000_1125 { + opp-microvolt = <1125000 1125000 1125000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi new file mode 100644 index 000000000000..c878f4231791 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@216000000_750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0003>; + opp-hz = /bits/ 64 <216000000>; + }; + + opp@216000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0004>; + opp-hz = /bits/ 64 <216000000>; + }; + + opp@312000000_750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0003>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@312000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0F 0x0004>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@456000000_750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x0C 0x0003>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@456000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@456000000_800_2_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@456000000_800_3_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@456000000_825 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@608000000_750 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0006>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_800_3_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_825 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@760000000_775 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0006>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_875_1_1 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_875_0_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_875_1_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_975 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@816000000_800 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@816000000_850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@816000000_875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0005>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@816000000_950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0006>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@816000000_1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@912000000_850 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_925 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0006>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_950_0_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0004>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_950_2_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@912000000_1050 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@1000000000_875 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0007>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_900 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_950 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0006>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1000_0_2 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1025 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1100 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1200000000_1000 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1050 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1100 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x02 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1125 { + clock-latency-ns = <400000>; + opp-supported-hw = <0x01 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 8861e0976e37..85fce5bc72d6 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -3,6 +3,8 @@ #include <dt-bindings/input/input.h> #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" / { model = "Toshiba AC100 / Dynabook AZ"; @@ -337,18 +339,26 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "+1.2vs_sm0,vdd_core"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 450000>; regulator-always-on; + + nvidia,tegra-core-regulator; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1100000>; + regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; + regulator-coupled-max-spread = <450000 450000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; sm2_reg: sm2 { @@ -367,10 +377,15 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "+1.2vs_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 450000>; + regulator-always-on; + + nvidia,tegra-rtc-regulator; }; ldo3 { @@ -603,4 +618,16 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 3e5ac096d85e..8debd3d3c20d 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -3,6 +3,7 @@ #include <dt-bindings/input/input.h> #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" / { model = "Compulab TrimSlice board"; @@ -471,4 +472,14 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8c942e60703e..9c58e7fcf5c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -851,12 +851,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 02f8126481a2..8b7a827d604d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -994,11 +994,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -1008,17 +1014,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; /* diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7f112f192fe9..c18f6f61d764 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -976,11 +976,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -990,17 +996,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; /* diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 4dbd4af679f0..9234988624ec 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */ @@ -103,4 +105,50 @@ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; }; + + i2c@7000d000 { + pmic: tps65911@2d { + regulators { + vddctrl_reg: vddctrl { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vddcore_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + + nvidia,tegra-cpu-regulator; + }; + }; + }; + + vddcore_reg: tps62361@60 { + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + + nvidia,tegra-core-regulator; + }; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 35af03ca9e90..1f9198bb24ff 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -845,11 +845,18 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* forbid to use ADC channels 3-0 (touch) */ stmpe_touchscreen { compatible = "st,stmpe-ts"; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -859,17 +866,16 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; }; /* diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi new file mode 100644 index 000000000000..5c40ef49894f --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + opp@51000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@51000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@51000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@102000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@102000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@102000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@204000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@204000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@204000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@312000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@312000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@340000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@340000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@370000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@456000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@456000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@475000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@475000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@608000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@608000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@620000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_4_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_4_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_2 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_3 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_4_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_4_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_0_10 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@760000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@816000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@816000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@860000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@860000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_4_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_4_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@910000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1000000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1000000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_4_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_4_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1000000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1100000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1100000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_4_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_4_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_1 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_2 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_3 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_4 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1100000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1150000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1200000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1200000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_1 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_2 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_3 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_4 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_4_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_4_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_1 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_2 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_3 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_4 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_7 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_8 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1200000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1200000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1300000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1000_4_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1000_4_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_1 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_7 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_8 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_1 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_2 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_3 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_4 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_5 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_6 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_7 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_8 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_12 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_13 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_2 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_3 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_4 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1300000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1300000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1300000000_1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp@1400000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1400000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1400000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1400000000_1150_2_4 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1400000000_1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp@1400000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1500000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_5 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_6 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_12 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_13 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_5 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_6 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_12 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_13 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1200 { + opp-microvolt = <1200000 1200000 1250000>; + }; + + opp@1500000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1600000000_1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp@1600000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1700000000_1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp@1700000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi new file mode 100644 index 000000000000..d64fc262585e --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -0,0 +1,1202 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@51000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp@51000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp@51000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <51000000>; + }; + + opp@102000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp@102000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp@102000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <102000000>; + }; + + opp@204000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x31FE>; + opp-hz = /bits/ 64 <204000000>; + }; + + opp@204000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C01>; + opp-hz = /bits/ 64 <204000000>; + }; + + opp@204000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <204000000>; + }; + + opp@312000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C00>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@312000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@340000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0192>; + opp-hz = /bits/ 64 <340000000>; + }; + + opp@340000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>; + opp-hz = /bits/ 64 <340000000>; + }; + + opp@370000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x306C>; + opp-hz = /bits/ 64 <370000000>; + }; + + opp@456000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0C00>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@456000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@475000000_800 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x31FE>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@475000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@475000000_850_0_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@475000000_850_0_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@475000000_850_0_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0080>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@475000000_850_0_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0100>; + opp-hz = /bits/ 64 <475000000>; + }; + + opp@608000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0400>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@608000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@620000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x306C>; + opp-hz = /bits/ 64 <620000000>; + }; + + opp@640000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0F 0x0001>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_1_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_1_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_1_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0080>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_1_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0100>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_850_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@640000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <640000000>; + }; + + opp@760000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1E 0x3461>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_850_0_10 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0400>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0008>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0080>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_1_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0100>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_900_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@816000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0400>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@816000000_912 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@860000000_850 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0C 0x0001>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_900_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0004>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0008>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0080>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_975_1_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0100>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@860000000_1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@910000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x3060>; + opp-hz = /bits/ 64 <910000000>; + }; + + opp@1000000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x0C 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1100000000_900 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x06 0x0001>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_975_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1000_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1100000000_1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1150000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x3060>; + opp-hz = /bits/ 64 <1150000000>; + }; + + opp@1200000000_975 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1000_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1025_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1050 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1300000000_1000 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1000_4_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0080>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1000_4_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0100>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1025 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1025_3_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0002>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1025_3_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0080>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1025_3_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0100>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x12 0x3061>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_2_1 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0004>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0008>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_5 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0020>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_6 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0040>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_2_7 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0080>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_2_8 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0100>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_12 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x1000>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050_3_13 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x2000>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1075 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0182>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1075_2_2 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0004>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1075_2_3 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0008>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1075_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x001C>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0182>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1175 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1400000000_1100 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x18 0x307C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x000C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x000C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1150_2_4 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1175 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1500000000_1125 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1125_4_5 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0020>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1125_4_6 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x0040>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1125_4_12 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x1000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1125_4_13 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x2000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150_3_5 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0020>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150_3_6 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x0040>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150_3_12 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x1000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150_3_13 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x2000>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1200 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1600000000_1212 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1600000000>; + }; + + opp@1600000000_1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1600000000>; + }; + + opp@1700000000_1212 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + + opp@1700000000_1237 { + clock-latency-ns = <100000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index e074258d4518..55ae050042ce 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -422,6 +422,7 @@ clocks = <&tegra_car TEGRA30_CLK_VDE>; reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; + iommus = <&mc TEGRA_SWGROUP_VDE>; }; apbmisc@70000800 { @@ -732,6 +733,15 @@ #reset-cells = <1>; }; + memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + + nvidia,memory-controller = <&mc>; + }; + fuse@7000f800 { compatible = "nvidia,tegra30-efuse"; reg = <0x7000f800 0x400>; @@ -997,24 +1007,28 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; }; |