diff options
| author | Zong Li <[email protected]> | 2020-12-09 17:49:15 +0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-12-16 12:23:12 -0800 |
| commit | 263ac3908516abb0392747bbf595af2b13df5fa2 (patch) | |
| tree | fa1e098874aa90289427d2c09b191b59930602f0 | |
| parent | efc91ae43c8d4bbf64e4b9a28113b24a74ffd58d (diff) | |
clk: sifive: Fix the wrong bit field shift
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li <[email protected]>
Reported-by: Pragnesh Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
| -rw-r--r-- | drivers/clk/sifive/sifive-prci.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 7e509dfb72d1..88493f3b9edf 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -59,7 +59,7 @@ /* DDRPLLCFG1 */ #define PRCI_DDRPLLCFG1_OFFSET 0x10 -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) /* GEMGXLPLLCFG0 */ @@ -81,7 +81,7 @@ /* GEMGXLPLLCFG1 */ #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24 +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) /* CORECLKSEL */ |