diff options
| author | Paul Burton <[email protected]> | 2015-09-22 11:12:15 -0700 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2015-11-11 08:35:11 +0100 |
| commit | 252d6aa605fa05b559347d3ed0a4f11bbdf6d3d0 (patch) | |
| tree | 6f0c90c6a964f8abe340176cb8f6dd48e1ec7ea4 | |
| parent | a8c20614b0163a71f2df3f9788bfe8b9ff07d742 (diff) | |
MIPS: CM: Fix GCR_Cx_CONFIG PVPE mask
The PVPE (or PVP in >= CM3) field is 10 bits wide, but the mask
previously only covered the bottom 9 bits. Extend the mask to cover all
10 bits of the field.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: James Hogan <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11206/
Signed-off-by: Ralf Baechle <[email protected]>
| -rw-r--r-- | arch/mips/include/asm/mips-cm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 9261c003990a..7740c4f44289 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -359,7 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 -#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) +#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x3ff) << 0) /* GCR_Cx_OTHER register fields */ #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 |