diff options
| author | Ben Skeggs <[email protected]> | 2014-02-22 00:19:19 +1000 |
|---|---|---|
| committer | Ben Skeggs <[email protected]> | 2014-03-26 14:00:41 +1000 |
| commit | 22a7a27b18470db9435d5ac7fb1de42bde52061f (patch) | |
| tree | 080c9ad6b2bec7249607a95609dcb9b22f9b0136 | |
| parent | 0357466d7ec76181e076f98e15bfcf3f88b034aa (diff) | |
drm/nvc0/fifo: mask unhandled intr bits when seen, rather than all intrs
Signed-off-by: Ben Skeggs <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index 919980d902d1..5472f01272e9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c @@ -594,9 +594,9 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat) { - nv_fatal(priv, "unhandled status 0x%08x\n", stat); + nv_error(priv, "INTR 0x%08x\n", stat); + nv_mask(priv, 0x002140, stat, 0x00000000); nv_wr32(priv, 0x002100, stat); - nv_wr32(priv, 0x002140, 0); } } |