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authorBrian Masney <[email protected]>2019-11-21 20:26:45 -0500
committerRob Clark <[email protected]>2020-01-02 14:23:48 -0800
commit21f5a6c08b171b8ffd12d921facfe4597c0aa934 (patch)
treee9c562de458d8134e8715c8944bcfd7b5996ac24
parentd163ba0b65f2e46d6010625fa6603c93951a010f (diff)
drm/msm/a4xx: set interconnect bandwidth vote
Set the two interconnect paths for the GPU to maximum speed for now to work towards getting the GPU working upstream. We can revisit a later time to optimize this for battery life. Signed-off-by: Brian Masney <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Rob Clark <[email protected]>
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx_gpu.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index b01388a9e89e..253d8d85daad 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -591,6 +591,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
goto fail;
}
+ /*
+ * Set the ICC path to maximum speed for now by multiplying the fastest
+ * frequency by the bus width (8). We'll want to scale this later on to
+ * improve battery life.
+ */
+ icc_set_bw(gpu->icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
+ icc_set_bw(gpu->ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);
+
return gpu;
fail: