diff options
| author | Thomas Petazzoni <[email protected]> | 2017-03-07 16:53:19 +0100 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2017-03-09 10:12:11 -0800 |
| commit | 2067e0a13cfe0b1bdca7b91bc5e4f2740b07d478 (patch) | |
| tree | 99dd7056e7a27245cc00484649538d9ac85aeb32 | |
| parent | fceb55d41508c01ac05f1c9382d7efddcdf71409 (diff) | |
net: mvpp2: set dma mask and coherent dma mask on PPv2.2
On PPv2.2, the streaming mappings can be anywhere in the first 40 bits
of the physical address space. However, for the coherent mappings, we
still need them to be in the first 32 bits of the address space,
because all BM pools share a single register to store the high 32 bits
of the BM pool address, which means all BM pools must be allocated in
the same 4GB memory area.
Signed-off-by: Thomas Petazzoni <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 0a3c47017809..92c47f35bbdb 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -6941,6 +6941,20 @@ static int mvpp2_probe(struct platform_device *pdev) /* Get system's tclk rate */ priv->tclk = clk_get_rate(priv->pp_clk); + if (priv->hw_version == MVPP22) { + err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + if (err) + goto err_mg_clk; + /* Sadly, the BM pools all share the same register to + * store the high 32 bits of their address. So they + * must all have the same high 32 bits, which forces + * us to restrict coherent memory to DMA_BIT_MASK(32). + */ + err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (err) + goto err_mg_clk; + } + /* Initialize network controller */ err = mvpp2_init(pdev, priv); if (err < 0) { |