diff options
| author | Suniel Mahesh <[email protected]> | 2020-11-09 23:40:14 +0530 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2020-11-30 02:37:13 +0100 |
| commit | 1cc1e851d15b4ebd4c6c5f741cfdb58b988a4445 (patch) | |
| tree | 0bbb30ce4547ec74c78b2d39548304850f75f3bb | |
| parent | 93a4e7d12468b0ab46796f3ed8dc5838dc7f63bc (diff) | |
arm64: dts: rockchip: Add BT support on px30-engicam
Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the UART bus.
UART bus on the design routed via USB to UART CP20x bridge. This
bridge powered from 3V3 regualtor gpio.
This patch adds BT enablement nodes for these respective boards.
Signed-off-by: Michael Trimarchi <[email protected]>
Signed-off-by: Suniel Mahesh <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
3 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 0e1a93ec3234..08b0b9fbcbc9 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -24,6 +24,18 @@ pinctrl-0 = <&wifi_enable_h>; }; + vcc3v3_btreg: vcc3v3-btreg { + compatible = "regulator-gpio"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + regulator-name = "btreg-gpio-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + states = <3300000 0x0>; + }; + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { compatible = "regulator-fixed"; regulator-name = "vcc3v3_rf_aux_mod"; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index d5708779c285..bf10a3d29fca 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -8,6 +8,12 @@ #include "px30-engicam-common.dtsi" &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -18,3 +24,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index 913444548b59..d759478e1c84 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -21,6 +21,12 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -31,3 +37,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +}; |