diff options
| author | Yassine Oudjana <[email protected]> | 2022-06-21 20:06:16 +0400 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-09-26 11:12:35 -0500 |
| commit | 1ba0a3bbd5ed5a1bb8d0165912d9904b812af74b (patch) | |
| tree | 0fdea167bdc031078372cb4563100917f9f5258e | |
| parent | 94a70c873d56e8bb7bce52cfb68d004be174dfff (diff) | |
clk: qcom: msm8996-cpu: Rename DIV_2_INDEX to SMUX_INDEX
The parent at this index is the secondary mux, which can connect
not only to primary PLL/2 but also to XO. Rename the index to SMUX_INDEX
to better reflect the parent.
Signed-off-by: Yassine Oudjana <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | drivers/clk/qcom/clk-cpu-8996.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 4a4fde8dd12d..5dc68dc3621f 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -61,7 +61,7 @@ #include "clk-regmap.h" enum _pmux_input { - DIV_2_INDEX = 0, + SMUX_INDEX = 0, PLL_INDEX, ACD_INDEX, ALT_INDEX, @@ -468,7 +468,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, case POST_RATE_CHANGE: if (cnd->new_rate < DIV_2_THRESHOLD) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, - DIV_2_INDEX); + SMUX_INDEX); else ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); |