diff options
| author | Ilpo Järvinen <[email protected]> | 2023-09-15 18:57:46 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2023-10-10 16:03:51 -0500 |
| commit | 1a11074be2e94736d12e49a9a562b0a54e8a423d (patch) | |
| tree | b49c92fe3f40a995138da1300c9c8da42ab220c3 | |
| parent | 0bb80ecc33a8fb5a682236443c1e740d5c917d1d (diff) | |
PCI: Add PCI_L1SS_CTL2 fields
Add L1 PM Substates Control 2 Register fields (PCI_L1SS_CTL2_*).
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ilpo Järvinen <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e5f558d96493..3a7ea9581568 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1088,6 +1088,8 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +#define PCI_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ +#define PCI_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */ |