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authorLucas De Marchi <[email protected]>2023-09-27 12:38:57 -0700
committerRodrigo Vivi <[email protected]>2023-12-21 11:41:20 -0500
commit194bdb859950a4223305ee766a3b9d90c398d158 (patch)
tree54a41a20f33d80a4e59cdc2b42cc51082d5bc53a
parentb445be5710200501bba693fe6f9c614895412b94 (diff)
drm/xe/dg2: Fix using wrong PAT table
DG2 should use the MCR variant to program the PAT registers, like PVC, but shouldn't use the same table as PVC. Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
-rw-r--r--drivers/gpu/drm/xe/xe_pat.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 28f401c500d8..a4bebdedbbd9 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -108,10 +108,18 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.ops = &mtl_pat_ops;
xe->pat.table = mtl_pat_table;
xe->pat.n_entries = ARRAY_SIZE(mtl_pat_table);
- } else if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2) {
+ } else if (xe->info.platform == XE_PVC) {
xe->pat.ops = &dg2_pat_ops;
xe->pat.table = pvc_pat_table;
xe->pat.n_entries = ARRAY_SIZE(pvc_pat_table);
+ } else if (xe->info.platform == XE_DG2) {
+ /*
+ * Table is the same as previous platforms, but programming
+ * method has changed.
+ */
+ xe->pat.ops = &dg2_pat_ops;
+ xe->pat.table = tgl_pat_table;
+ xe->pat.n_entries = ARRAY_SIZE(tgl_pat_table);
} else if (GRAPHICS_VERx100(xe) <= 1210) {
xe->pat.ops = &tgl_pat_ops;
xe->pat.table = tgl_pat_table;