diff options
| author | Ville Syrjälä <[email protected]> | 2022-11-23 17:26:27 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2022-12-13 05:12:24 +0200 |
| commit | 1867fcebd7a728d15a5c2352933d5731b0eca7f5 (patch) | |
| tree | 7579fe9edd7814b1d525a8fda2fbf638637dba31 | |
| parent | 07e176f2ad357a9371b9e9a80fc1c77016399ddf (diff) | |
drm/i915: Clean up GAMMA_MODE defines
Use REG_BIT() & co. for GAMMA_MODE bits.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Ankit Nautiyal <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab39cfb14a19..6c91e42540cb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5308,14 +5308,14 @@ #define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) -#define PRE_CSC_GAMMA_ENABLE (1 << 31) -#define POST_CSC_GAMMA_ENABLE (1 << 30) -#define GAMMA_MODE_MODE_MASK (3 << 0) -#define GAMMA_MODE_MODE_8BIT (0 << 0) -#define GAMMA_MODE_MODE_10BIT (1 << 0) -#define GAMMA_MODE_MODE_12BIT (2 << 0) -#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ -#define GAMMA_MODE_MODE_12BIT_MULTI_SEG (3 << 0) /* icl-tgl */ +#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ +#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ +#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) +#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) +#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) +#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) +#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ +#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ /* Display Internal Timeout Register */ #define RM_TIMEOUT _MMIO(0x42060) |