diff options
| author | Aidan Wood <[email protected]> | 2019-03-22 14:45:12 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-06-22 09:34:08 -0500 |
| commit | 173932dec76fbf9f8e5a75a74ccbffc186ce0a4a (patch) | |
| tree | 73469dccf0ed3c855935288be3f7c0d2f11beee5 | |
| parent | c2ad17c3b2657b476044582e875c88b750011bba (diff) | |
drm/amd/display: Properly set u clock
[Why]
u clk set request was being sent in units of mts, when it needed to be
in units of Mhz
[How]
add a division by 16 to convert from mts to Mhz
Signed-off-by: Aidan Wood <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 6bc4b3f3301f..7aa2859b35fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2132,7 +2132,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000; + context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; context->bw_ctx.bw.dcn.clk.p_state_change_support = |