diff options
| author | Biju Das <[email protected]> | 2022-09-19 09:41:10 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-10-17 10:03:59 +0200 |
| commit | 1625fbc1f73f1fa8f77c38ea554cc0b2327b156b (patch) | |
| tree | 6e11e2a3a9f35cae2b74232a62daae1889cb32ba | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
clk: renesas: rzg2l: Support sd clk mux round operation
Currently, determine_rate() is not doing any round operation
and due to this it always selects a lower clock source compared
to the closest higher one.
Support sd clk mux round operation by passing
CLK_MUX_ROUND_CLOSEST flag to clk_mux_determine_rate_flags().
Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3ff6ecd61756..5dfe3624f681 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -182,7 +182,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - return clk_mux_determine_rate_flags(hw, req, 0); + return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); } static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) |