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authorDmitry Baryshkov <[email protected]>2023-05-13 00:17:23 +0300
committerBjorn Andersson <[email protected]>2023-07-31 14:25:17 -0700
commit1583694bb4eaf186f17131dbc1b83d6057d2749b (patch)
tree3b7f3d64baf13c4ee0808c16023d4aa5ba39ecf4
parentbac4675a4d1b80cd69eef311c6c112a88e5845f5 (diff)
clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock
The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: [email protected] Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r--drivers/clk/qcom/gcc-mdm9615.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index fb5c1244fb97..2f921891008d 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
- .parent_names = (const char *[]){ "pll8" },
+ .parent_names = (const char *[]){ "pll0" },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},