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authorMichael Straube <[email protected]>2021-08-14 09:39:20 +0200
committerGreg Kroah-Hartman <[email protected]>2021-08-16 09:09:04 +0200
commit11fc4822f9c08c80c55df2303a8b9c42566b74b8 (patch)
treed7f5cf919266c13726866df06e61e1b98a81f677
parenta4adfa836c5289df905af19edc9727fc275dc1a1 (diff)
staging: r8188eu: remove ODM_GetRightChnlPlaceforIQK()
Function ODM_GetRightChnlPlaceforIQK() returns always zero for channels <= 14. The driver is for chips that do not support 5 GHz, so remove the function and replace the usage of its return value with zero. Acked-by: Fabio M. De Francesco <[email protected]> Acked-by: Phillip Potter <[email protected]> Signed-off-by: Michael Straube <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
-rw-r--r--drivers/staging/r8188eu/hal/HalPhyRf_8188e.c29
1 files changed, 3 insertions, 26 deletions
diff --git a/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
index 643a4d348b2e..c92a76aebc11 100644
--- a/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
+++ b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c
@@ -1004,27 +1004,6 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t,
}
}
-#define ODM_TARGET_CHNL_NUM_2G_5G 59
-static u8 ODM_GetRightChnlPlaceforIQK(u8 chnl)
-{
- u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
- 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
- 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153,
- 155, 157, 159, 161, 163, 165
- };
- u8 place = chnl;
-
- if (chnl > 14) {
- for (place = 14; place < sizeof(channel_all); place++) {
- if (channel_all[place] == chnl)
- return place-13;
- }
- }
- return 0;
-}
-
static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
{
u8 tmpreg;
@@ -1088,7 +1067,7 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
struct mpt_context *pMptCtx = &adapt->mppriv.MptCtx;
s32 result[4][8]; /* last is final result */
- u8 i, final_candidate, Indexforchannel;
+ u8 i, final_candidate;
bool pathaok, pathbok;
s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC, RegEC4;
bool is12simular, is13simular, is23simular;
@@ -1200,14 +1179,12 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
pathb_fill_iqk(adapt, pathbok, result, final_candidate, (RegEC4 == 0));
}
- Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
-
/* To Fix BSOD when final_candidate is 0xff */
/* by sherry 20120321 */
if (final_candidate < 4) {
for (i = 0; i < IQK_Matrix_REG_NUM; i++)
- dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
- dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = true;
+ dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final_candidate][i];
+ dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true;
}
_PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);