aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKrzysztof Kozlowski <[email protected]>2023-04-22 00:32:01 +0200
committerKrzysztof Kozlowski <[email protected]>2023-07-13 08:44:15 +0200
commit1193001081e98d13c786fe0cae407cb747104cdc (patch)
treefd6612bc8cda4405e93f9fc25c3203f5af8350a5
parenta8cf500c42c751b992f5480c390d6ad2419472e0 (diff)
arm64: dts: lg: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: lg1312-ref.dtb: l2-cache0: 'cache-level' is a required property Acked-by: Chanho Min <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
-rw-r--r--arch/arm64/boot/dts/lg/lg1312.dtsi2
-rw-r--r--arch/arm64/boot/dts/lg/lg1313.dtsi2
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 78ae73d0cf36..48ec4ebec0a8 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -48,6 +48,8 @@
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 2173316573be..3869460aa5dc 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -48,6 +48,8 @@
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};