diff options
| author | Narayanan <[email protected]> | 2011-09-13 17:00:22 +0530 |
|---|---|---|
| committer | Fabio Baltieri <[email protected]> | 2013-01-14 10:50:09 +0100 |
| commit | 0fd602235dd702d16722857da748d15c26b81ed1 (patch) | |
| tree | ee767fd8fdfcddb785629c755866271aca08227c | |
| parent | d1c3ed669a2d452cacfb48c2d171a1f364dae2ed (diff) | |
dmaengine: ste_dma40: reset priority bit for logical channels
This patch sets the SSCFG/SDCFG bit[7] PRI only for physical channel
requests with high priority. For logical channels, this bit will be
zero.
Signed-off-by: Narayanan G <[email protected]>
Reviewed-by: Rabin Vincent <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Signed-off-by: Fabio Baltieri <[email protected]>
| -rw-r--r-- | drivers/dma/ste_dma40_ll.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c index 851ad56e8409..d64b72ae2dc8 100644 --- a/drivers/dma/ste_dma40_ll.c +++ b/drivers/dma/ste_dma40_ll.c @@ -102,17 +102,18 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS; dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS; + /* Set the priority bit to high for the physical channel */ + if (cfg->high_priority) { + src |= 1 << D40_SREG_CFG_PRI_POS; + dst |= 1 << D40_SREG_CFG_PRI_POS; + } + } else { /* Logical channel */ dst |= 1 << D40_SREG_CFG_LOG_GIM_POS; src |= 1 << D40_SREG_CFG_LOG_GIM_POS; } - if (cfg->high_priority) { - src |= 1 << D40_SREG_CFG_PRI_POS; - dst |= 1 << D40_SREG_CFG_PRI_POS; - } - if (cfg->src_info.big_endian) src |= 1 << D40_SREG_CFG_LBE_POS; if (cfg->dst_info.big_endian) |