diff options
| author | Kaushal Kumar <[email protected]> | 2022-05-02 10:08:04 -0700 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-06-27 16:08:49 -0500 |
| commit | 0ec15b6f7621c2e5ded3d3d1a67361da1895c26b (patch) | |
| tree | b70dbad934ee1f7de8a011eca6623a7a8055f6c0 | |
| parent | ab11b74d87ddadb1e6e6d8dc36f3145a26158ef2 (diff) | |
ARM: dts: qcom: sdx65: Add QPIC NAND support
Add devicetree node to enable support for QPIC
NAND controller on Qualcomm SDX65 platform.
Since there is no "aon" clock in SDX65, a dummy
clock is provided.
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Kaushal Kumar <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 91c9dc18fe3a..7fd75c441289 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -204,6 +210,22 @@ status = "disabled"; }; + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; |