diff options
| author | Adam Ford <[email protected]> | 2021-02-24 05:51:45 -0600 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-05-25 09:55:52 +0200 |
| commit | 0decd50b6b2ef085f3f6c018b5e7eb8ba627b11e (patch) | |
| tree | d2f3033f78548aa865268410b6ad981dea39b1fb | |
| parent | 56ed0b3b10fd2814cb8225c420000a51bb202e31 (diff) | |
arm64: dts: renesas: beacon kit: Setup AVB refclk
The AVB reference clock assumes an external clock that runs
automatically. Because the Versaclock is wired to provide the
AVB refclock, the device tree needs to reference it in order for the
driver to start the clock.
Signed-off-by: Adam Ford <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 8d3a4d6ee885..75355c354c38 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -53,6 +53,8 @@ phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; + clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; + clock-names = "fck", "refclk"; status = "okay"; phy0: ethernet-phy@0 { |