diff options
| author | Mario Limonciello <[email protected]> | 2023-07-05 08:30:02 -0500 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2023-07-13 00:04:02 +0200 |
| commit | 0d5ace1a07f7e846d0f6d972af60d05515599d0b (patch) | |
| tree | 31fb5d33561e41fd731b7525b253798aa0d6297b | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
pinctrl: amd: Only use special debounce behavior for GPIO 0
It's uncommon to use debounce on any other pin, but technically
we should only set debounce to 0 when working off GPIO0.
Cc: [email protected]
Tested-by: Jan Visser <[email protected]>
Fixes: 968ab9261627 ("pinctrl: amd: Detect internal GPIO0 debounce handling")
Signed-off-by: Mario Limonciello <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3c4220be30ec..00d5b517b745 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -128,9 +128,11 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, raw_spin_lock_irqsave(&gpio_dev->lock, flags); /* Use special handling for Pin0 debounce */ - pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); - if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) - debounce = 0; + if (offset == 0) { + pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) + debounce = 0; + } pin_reg = readl(gpio_dev->base + offset * 4); |