diff options
| author | Parthiban Nallathambi <[email protected]> | 2024-05-25 22:48:53 +0530 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2024-06-16 10:26:28 +0800 |
| commit | 0ce551af516a8d7361b7254ce5c742380f68284c (patch) | |
| tree | d1a0c29fd40aaa33946a609bf7cc35e4826c1faf | |
| parent | 044786935ec5f051c4bd1baef7831dd4bfb5ad52 (diff) | |
arm64: dts: phygate-tauri-l: enable pcie phy
I210 intel ethernet controller is connected to PCIe. Enable the PHY
to use the ethernet controller.
Signed-off-by: Parthiban Nallathambi <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index 27a902569e2a..ba6ce3c7f477 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -7,6 +7,7 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include "imx8mm-phycore-som.dtsi" / { @@ -185,6 +186,15 @@ status = "okay"; }; +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; |