diff options
| author | Vinod Polimera <[email protected]> | 2022-03-22 08:57:10 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-06-24 12:07:31 -0500 |
| commit | 0b24829fd74cf954b3a02e9e4c4da3c098c69fbc (patch) | |
| tree | d18fa5e8d9b6467c343d0ac03d7771a1cfda02da | |
| parent | aa4ae511a760e66f22641d9b9b6052b469df3c10 (diff) | |
arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].
[1] https://lore.kernel.org/r/[email protected]/
Signed-off-by: Vinod Polimera <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0692ae0e60a4..d9d292f1ef38 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4248,9 +4248,6 @@ <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; @@ -4281,10 +4278,8 @@ <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; |