diff options
| author | Kan Liang <[email protected]> | 2020-01-28 10:31:19 -0800 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2020-02-11 13:17:50 +0100 |
| commit | 0aa0e0d6b34b89649e6b5882a7e025a0eb9bd832 (patch) | |
| tree | f20e489f58d062ea1a8c7b8e7484639fa961f07c | |
| parent | ecf71fbccb9ac5cb964eb7de59bb9da3755b7885 (diff) | |
perf/x86/msr: Add Tremont support
Tremont is Intel's successor to Goldmont Plus. SMI_COUNT MSR is also
supported.
Signed-off-by: Kan Liang <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Reviewed-by: Andi Kleen <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
| -rw-r--r-- | arch/x86/events/msr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 6f86650b3f77..a949f6f55991 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -75,8 +75,9 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT: case INTEL_FAM6_ATOM_GOLDMONT_D: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_FAM6_ATOM_TREMONT_D: + case INTEL_FAM6_ATOM_TREMONT: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |