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authorJustin Swartz <[email protected]>2024-03-16 06:54:30 +0200
committerThomas Bogendoerfer <[email protected]>2024-04-15 10:23:36 +0200
commit09e8ff7576ae9dd4996172d3bf18975c73f3dc77 (patch)
tree03592a745407905c0f3fcc9af8989facb3dfd94d
parent3eee9ac24cef892e6883b3669544c6101b70c91e (diff)
mips: dts: ralink: mt7621: reorder cpuintc node attributes
Reorder the CPU Interrupt Controller node's attributes to follow what the DTS Coding Style dictates. Signed-off-by: Justin Swartz <[email protected]> Reviewed-by: Arınç ÜNAL <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 73dad64e11fe..ec87e46ba6de 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -27,10 +27,12 @@
};
cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+
#address-cells = <0>;
#interrupt-cells = <1>;
+
interrupt-controller;
- compatible = "mti,cpu-interrupt-controller";
};
mmc_fixed_3v3: regulator-3v3 {