diff options
| author | Janakarajan Natarajan <[email protected]> | 2018-11-07 20:59:07 +0000 |
|---|---|---|
| committer | Borislav Petkov <[email protected]> | 2018-11-07 22:21:03 +0100 |
| commit | 08e823c2c5899ef2de3aa1727233f1f19e8c1cc1 (patch) | |
| tree | 9fc0073dea3de144a8a3ffd8b0ab1c328e2db784 | |
| parent | 43500e6f294d175602606c77bfb0d8cd4ea88b4f (diff) | |
x86/cpufeatures: Add WBNOINVD feature definition
Add a new cpufeature definition for the WBNOINVD instruction.
The WBNOINVD instruction writes all modified cache lines in all levels of
the cache associated with a processor to main memory while retaining the
cached values.
Both AMD and Intel support this instruction.
Signed-off-by: Janakarajan Natarajan <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
CC: David Woodhouse <[email protected]>
CC: Fenghua Yu <[email protected]>
CC: "H. Peter Anvin" <[email protected]>
CC: Ingo Molnar <[email protected]>
CC: Konrad Rzeszutek Wilk <[email protected]>
CC: Rudolf Marek <[email protected]>
CC: Thomas Gleixner <[email protected]>
CC: x86-ml <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 28c4a502b419..39a48f06d39d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -281,6 +281,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ |