diff options
author | Jacky Bai <[email protected]> | 2023-06-28 14:17:24 +0800 |
---|---|---|
committer | Abel Vesa <[email protected]> | 2023-07-25 10:28:42 +0300 |
commit | 07ba6d1ae524c627ac55bb98d5610d4fc44d3fe7 (patch) | |
tree | bc1b38a4f2f014079865080d1064f91763fbdc4a | |
parent | 3ea570486039a12bb9dcbec977c70390b3d3c902 (diff) |
clk: imx: Add 519.75MHz frequency support for imx9 pll
For video pll, it may need 519.75MHz clock frequency for
the LVDS display usage. So add 519.75MHz frequency config
support for video pll.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
-rw-r--r-- | drivers/clk/imx/clk-fracn-gppll.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index c54f9999da04..44462ab50e51 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), |