diff options
| author | Johan Hovold <[email protected]> | 2022-07-15 09:02:48 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-07-16 21:31:56 -0500 |
| commit | 079926b5a22ac92c4ac1e15e6cfb20a431802cb5 (patch) | |
| tree | cdfd80b49869078c6cc0e255c8f90a691a923048 | |
| parent | 5142c3926f8fd358a62810cf09adcb128904694b (diff) | |
ARM: dts: qcom: sdx65: reorder USB interrupts
Three SoCs did not follow the interrupt order specified by the USB
controller binding.
While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
[bjorn: Split out from arm64 patch]
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7a193678b4f5..8daefd50217a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -372,11 +372,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 18 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "ss_phy_irq", "dm_hs_phy_irq"; + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_GDSC>; |