diff options
| author | Allen-KH Cheng <[email protected]> | 2022-07-12 19:40:46 +0800 |
|---|---|---|
| committer | Matthias Brugger <[email protected]> | 2022-08-29 16:42:34 +0200 |
| commit | 0708ed7c2c63a60ee59dd50cdb50689571a234b3 (patch) | |
| tree | 91ccce55e020c26b97bd3da93e039ff56afcc049 | |
| parent | b4b75bac952bd5393cae4b58ad1986b569fd7231 (diff) | |
arm64: dts: mt8192: Add dsi node
Add dsi node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: Nícolas F. R. A. Prado <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Tested-by: Nícolas F. R. A. Prado <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matthias Brugger <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c8ae0285bb53..64bf65b1b184 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1344,6 +1344,25 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; + dsi0: dsi@14010000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + status = "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + ovl_2l2: ovl@14014000 { compatible = "mediatek,mt8192-disp-ovl-2l"; reg = <0 0x14014000 0 0x1000>; |