diff options
| author | Lina Iyer <[email protected]> | 2015-03-25 14:25:35 -0600 |
|---|---|---|
| committer | Olof Johansson <[email protected]> | 2015-04-03 13:33:55 -0700 |
| commit | 06c49f2b88eb177f4f96d68d561f28fb125e7c0c (patch) | |
| tree | 27893a7b037c5416501cda7c2f46e542d60c9c7f | |
| parent | d8664979e6ba97024c43d6248f94982ee0c8d1ee (diff) | |
ARM: dts: qcom: Add idle state device nodes for 8064
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 58e1d79185ce..6c1511263a55 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -23,6 +23,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; }; cpu@1 { @@ -33,6 +34,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_SPC>; }; cpu@2 { @@ -43,6 +45,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_SPC>; }; cpu@3 { @@ -53,12 +56,23 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", + "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; }; cpu-pmu { |