diff options
| author | Coiby Xu <[email protected]> | 2020-11-06 07:19:09 +0800 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2020-11-10 14:18:37 +0100 |
| commit | 06abe8291bc31839950f7d0362d9979edc88a666 (patch) | |
| tree | b68876f491e9818cad071f0e316e5b559734f4dd | |
| parent | 9b92f5c51e9a41352d665f6f956bd95085a56a83 (diff) | |
pinctrl: amd: fix incorrect way to disable debounce filter
The correct way to disable debounce filter is to clear bit 5 and 6
of the register.
Cc: [email protected]
Signed-off-by: Coiby Xu <[email protected]>
Reviewed-by: Hans de Goede <[email protected]>
Cc: Hans de Goede <[email protected]>
Link: https://lore.kernel.org/linux-gpio/[email protected]/
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9a760f5cd7ed..d6b2b4bd337c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); } else { - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); ret = -EINVAL; } } else { pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); pin_reg &= ~DB_TMR_OUT_MASK; - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); } writel(pin_reg, gpio_dev->base + offset * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |