diff options
| author | Heyi Guo <[email protected]> | 2020-02-25 17:00:23 +0800 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2020-03-08 14:25:46 +0000 |
| commit | 04d80dbe858d801efbecf3e5172b31b0a3757308 (patch) | |
| tree | 6a3bb01026b1cb74232f7e1a121845814388d7a0 | |
| parent | 47beed513a85b3561e74cbb4dd7af848716fa4e0 (diff) | |
irqchip/gic-v3-its: Fix access width for gicr_syncr
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | drivers/irqchip/irq-gic-v3-its.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 83b1186ffcad..6bb2bea0d5fb 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) static void wait_for_syncr(void __iomem *rdbase) { - while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) + while (readl_relaxed(rdbase + GICR_SYNCR) & 1) cpu_relax(); } |