diff options
| author | Andrzej Hajda <[email protected]> | 2022-11-14 11:38:24 +0100 |
|---|---|---|
| committer | Linus Torvalds <[email protected]> | 2022-11-30 08:44:00 -0800 |
| commit | 04aa64375f48a5d430b5550d9271f8428883e550 (patch) | |
| tree | edf677f29dd9a9eae66a7ac0ce57562354c780f7 | |
| parent | 01f856ae6d0ca5ad0505b79bf2d22d7ca439b2a1 (diff) | |
drm/i915: fix TLB invalidation for Gen12 video and compute engines
In case of Gen12 video and compute engines, TLB_INV registers are masked -
to modify one bit, corresponding bit in upper half of the register must
be enabled, otherwise nothing happens.
CVE: CVE-2022-4139
Suggested-by: Chris Wilson <[email protected]>
Signed-off-by: Andrzej Hajda <[email protected]>
Acked-by: Daniel Vetter <[email protected]>
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Cc: [email protected]
Signed-off-by: Linus Torvalds <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d0b03a928b9a..5c931b6696c3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1017,6 +1017,11 @@ static void mmio_invalidate_full(struct intel_gt *gt) if (!i915_mmio_reg_offset(rb.reg)) continue; + if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || + engine->class == VIDEO_ENHANCEMENT_CLASS || + engine->class == COMPUTE_CLASS)) + rb.bit = _MASKED_BIT_ENABLE(rb.bit); + intel_uncore_write_fw(uncore, rb.reg, rb.bit); awake |= engine->mask; } |