diff options
| author | Jean-Jacques Hiblot <[email protected]> | 2022-02-21 10:50:29 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-02-24 13:48:45 +0100 |
| commit | 045d0625d305b2c99aba60f787250483af4a23a4 (patch) | |
| tree | 90d56a5d3ca4dd0a39d9c701d32d3c4993651681 | |
| parent | a3a59919ab662682a2cb77b25b0f7b9e6c78737e (diff) | |
ARM: dts: r9a06g032: Add the watchdog nodes
This SoC includes 2 watchdog controllers (one per A7 core).
Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index db657224688a..636a6ab31c58 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -66,6 +66,22 @@ interrupt-parent = <&gic>; ranges; + wdt0: watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + sysctrl: system-controller@4000c000 { compatible = "renesas,r9a06g032-sysctrl"; reg = <0x4000c000 0x1000>; |