diff options
| author | Marc Zyngier <[email protected]> | 2020-11-12 18:00:30 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2020-11-27 11:40:32 +0000 |
| commit | 04355e41a60338206d6498fe463a86131d5ca06b (patch) | |
| tree | 8218d8e824bea7bb8c94adc0f0e6f833448e8a49 | |
| parent | 9bbfa4b565379eeb2fb8fdbcc9979549ae0e48d9 (diff) | |
KVM: arm64: Set ID_AA64DFR0_EL1.PMUVer to 0 when no PMU support
We always expose the HW view of PMU in ID_AA64FDR0_EL1.PMUver,
even when the PMU feature is disabled, while the architecture
says that FEAT_PMUv3 not being implemented should result in this
field being zero.
Let's follow the architecture's guidance.
Reviewed-by: Alexandru Elisei <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
| -rw-r--r-- | arch/arm64/kvm/sys_regs.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d2e1d745f067..6629cfde2838 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1070,10 +1070,15 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); } else if (id == SYS_ID_AA64DFR0_EL1) { + u64 cap = 0; + /* Limit guests to PMUv3 for ARMv8.1 */ + if (kvm_vcpu_has_pmu(vcpu)) + cap = ID_AA64DFR0_PMUVER_8_1; + val = cpuid_feature_cap_perfmon_field(val, ID_AA64DFR0_PMUVER_SHIFT, - ID_AA64DFR0_PMUVER_8_1); + cap); } else if (id == SYS_ID_DFR0_EL1) { /* Limit guests to PMUv3 for ARMv8.1 */ val = cpuid_feature_cap_perfmon_field(val, |