diff options
| author | Lionel Landwerlin <[email protected]> | 2017-08-03 17:58:07 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2017-08-03 18:17:47 +0100 |
| commit | 01d928e9a1644eb2e28f684905f888e700c7b9dc (patch) | |
| tree | e5410ae117517d5ee4d8d179acef3c24a5b710b3 | |
| parent | 59f3da1e0ecb48e28c2ff6ffed4c354997452e77 (diff) | |
drm/i915/perf: fix flex eu registers programming
We were reserving fewer dwords in the ring than necessary. Indeed
we're always writing all registers once, so discard the actual number
of registers given by the user and just program the whitelisted ones
once.
Fixes: 19f81df2859e ("drm/i915/perf: Add OA unit support for Gen 8+")
Reported-by: Matthew Auld <[email protected]>
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Matthew Auld <[email protected]>
Cc: <[email protected]> # v4.12+
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/i915_perf.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 96682fd86f82..df78bfa9e574 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) u32 *cs; int i; - cs = intel_ring_begin(req, n_flex_regs * 2 + 4); + cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1); + *cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1); *cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL); *cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) | |