diff options
| author | Kishon Vijay Abraham I <[email protected]> | 2014-07-14 16:12:20 +0530 |
|---|---|---|
| committer | Tony Lindgren <[email protected]> | 2014-07-15 00:16:12 -0700 |
| commit | 00b0af5b68fc8bde724f7d491099179253bc4da8 (patch) | |
| tree | 3aee1757bcc197cd3e83c7a5dfb28a2892165039 | |
| parent | b700f42c863e17569ca4d864e369210d9ff00b8a (diff) | |
ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak <[email protected]>
Cc: Tero Kristo <[email protected]>
Cc: Paul Walmsley <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Kumar Gala <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index fe5db55aeede..b48f18b234b3 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1173,6 +1173,14 @@ ti,bit-shift = <8>; }; + optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; @@ -1191,6 +1199,14 @@ ti,bit-shift = <9>; }; + optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <9>; + }; + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; @@ -1199,6 +1215,14 @@ ti,bit-shift = <10>; }; + optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 { + compatible = "ti,gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x13b8>; + ti,bit-shift = <10>; + }; + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; |