58fdb1c355
[ Upstream commit 1f5e307ca16c0c19186cbd56ac460a687e6daba0 ] The caching mode of an IOMMU is irrelevant to the behavior of the device TLB. Previously, commit <304b3bde24b5> ("iommu/vt-d: Remove caching mode check before device TLB flush") removed this redundant check in the domain unmap path. Checking the caching mode before flushing the device TLB after a pasid table entry is updated is unnecessary and can lead to inconsistent behavior. Extends this consistency by removing the caching mode check in the pasid table update path. Suggested-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20240820030208.20020-1-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
937 lines
24 KiB
C
937 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* intel-pasid.c - PASID idr, table and entry manipulation
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*
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* Copyright (C) 2018 Intel Corporation
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*
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* Author: Lu Baolu <baolu.lu@linux.intel.com>
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/bitops.h>
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#include <linux/cpufeature.h>
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#include <linux/dmar.h>
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#include <linux/iommu.h>
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#include <linux/memory.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include <linux/spinlock.h>
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#include "iommu.h"
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#include "pasid.h"
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#include "../iommu-pages.h"
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/*
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* Intel IOMMU system wide PASID name space:
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*/
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u32 intel_pasid_max_id = PASID_MAX;
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/*
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* Per device pasid table management:
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*/
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/*
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* Allocate a pasid table for @dev. It should be called in a
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* single-thread context.
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*/
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int intel_pasid_alloc_table(struct device *dev)
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{
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struct device_domain_info *info;
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struct pasid_table *pasid_table;
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struct pasid_dir_entry *dir;
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u32 max_pasid = 0;
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int order, size;
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might_sleep();
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info = dev_iommu_priv_get(dev);
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if (WARN_ON(!info || !dev_is_pci(dev)))
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return -ENODEV;
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if (WARN_ON(info->pasid_table))
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return -EEXIST;
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pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
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if (!pasid_table)
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return -ENOMEM;
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if (info->pasid_supported)
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max_pasid = min_t(u32, pci_max_pasids(to_pci_dev(dev)),
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intel_pasid_max_id);
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size = max_pasid >> (PASID_PDE_SHIFT - 3);
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order = size ? get_order(size) : 0;
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dir = iommu_alloc_pages_node(info->iommu->node, GFP_KERNEL, order);
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if (!dir) {
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kfree(pasid_table);
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return -ENOMEM;
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}
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pasid_table->table = dir;
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pasid_table->order = order;
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pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);
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info->pasid_table = pasid_table;
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if (!ecap_coherent(info->iommu->ecap))
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clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE);
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return 0;
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}
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void intel_pasid_free_table(struct device *dev)
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{
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struct device_domain_info *info;
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struct pasid_table *pasid_table;
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struct pasid_dir_entry *dir;
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struct pasid_entry *table;
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int i, max_pde;
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info = dev_iommu_priv_get(dev);
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if (!info || !dev_is_pci(dev) || !info->pasid_table)
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return;
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pasid_table = info->pasid_table;
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info->pasid_table = NULL;
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/* Free scalable mode PASID directory tables: */
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dir = pasid_table->table;
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max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT;
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for (i = 0; i < max_pde; i++) {
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table = get_pasid_table_from_pde(&dir[i]);
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iommu_free_page(table);
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}
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iommu_free_pages(pasid_table->table, pasid_table->order);
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kfree(pasid_table);
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}
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struct pasid_table *intel_pasid_get_table(struct device *dev)
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{
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struct device_domain_info *info;
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info = dev_iommu_priv_get(dev);
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if (!info)
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return NULL;
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return info->pasid_table;
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}
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static int intel_pasid_get_dev_max_id(struct device *dev)
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{
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struct device_domain_info *info;
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info = dev_iommu_priv_get(dev);
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if (!info || !info->pasid_table)
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return 0;
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return info->pasid_table->max_pasid;
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}
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static struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid)
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{
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struct device_domain_info *info;
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struct pasid_table *pasid_table;
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struct pasid_dir_entry *dir;
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struct pasid_entry *entries;
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int dir_index, index;
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pasid_table = intel_pasid_get_table(dev);
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if (WARN_ON(!pasid_table || pasid >= intel_pasid_get_dev_max_id(dev)))
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return NULL;
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dir = pasid_table->table;
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info = dev_iommu_priv_get(dev);
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dir_index = pasid >> PASID_PDE_SHIFT;
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index = pasid & PASID_PTE_MASK;
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retry:
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entries = get_pasid_table_from_pde(&dir[dir_index]);
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if (!entries) {
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u64 tmp;
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entries = iommu_alloc_page_node(info->iommu->node, GFP_ATOMIC);
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if (!entries)
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return NULL;
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/*
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* The pasid directory table entry won't be freed after
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* allocation. No worry about the race with free and
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* clear. However, this entry might be populated by others
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* while we are preparing it. Use theirs with a retry.
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*/
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tmp = 0ULL;
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if (!try_cmpxchg64(&dir[dir_index].val, &tmp,
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(u64)virt_to_phys(entries) | PASID_PTE_PRESENT)) {
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iommu_free_page(entries);
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goto retry;
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}
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if (!ecap_coherent(info->iommu->ecap)) {
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clflush_cache_range(entries, VTD_PAGE_SIZE);
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clflush_cache_range(&dir[dir_index].val, sizeof(*dir));
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}
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}
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return &entries[index];
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}
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/*
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* Interfaces for PASID table entry manipulation:
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*/
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static void
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intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore)
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{
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struct pasid_entry *pe;
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pe = intel_pasid_get_entry(dev, pasid);
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if (WARN_ON(!pe))
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return;
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if (fault_ignore && pasid_pte_is_present(pe))
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pasid_clear_entry_with_fpd(pe);
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else
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pasid_clear_entry(pe);
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}
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static void
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pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
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u16 did, u32 pasid)
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{
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struct qi_desc desc;
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desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
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QI_PC_PASID(pasid) | QI_PC_TYPE;
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desc.qw1 = 0;
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_submit_sync(iommu, &desc, 1, 0);
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}
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static void
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devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
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struct device *dev, u32 pasid)
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{
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struct device_domain_info *info;
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u16 sid, qdep, pfsid;
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info = dev_iommu_priv_get(dev);
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if (!info || !info->ats_enabled)
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return;
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if (pci_dev_is_disconnected(to_pci_dev(dev)))
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return;
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sid = info->bus << 8 | info->devfn;
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qdep = info->ats_qdep;
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pfsid = info->pfsid;
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/*
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* When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID),
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* devTLB flush w/o PASID should be used. For non-zero PASID under
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* SVA usage, device could do DMA with multiple PASIDs. It is more
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* efficient to flush devTLB specific to the PASID.
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*/
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if (pasid == IOMMU_NO_PASID)
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qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
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else
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qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT);
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}
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void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,
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u32 pasid, bool fault_ignore)
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{
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struct pasid_entry *pte;
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u16 did, pgtt;
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (WARN_ON(!pte) || !pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return;
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}
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did = pasid_get_domain_id(pte);
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pgtt = pasid_pte_get_pgtt(pte);
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intel_pasid_clear_entry(dev, pasid, fault_ignore);
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spin_unlock(&iommu->lock);
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if (!ecap_coherent(iommu->ecap))
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clflush_cache_range(pte, sizeof(*pte));
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pasid_cache_invalidation_with_pasid(iommu, did, pasid);
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if (pgtt == PASID_ENTRY_PGTT_PT || pgtt == PASID_ENTRY_PGTT_FL_ONLY)
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qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
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else
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iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
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devtlb_invalidation_with_pasid(iommu, dev, pasid);
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}
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/*
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* This function flushes cache for a newly setup pasid table entry.
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* Caller of it should not modify the in-use pasid table entries.
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*/
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static void pasid_flush_caches(struct intel_iommu *iommu,
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struct pasid_entry *pte,
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u32 pasid, u16 did)
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{
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if (!ecap_coherent(iommu->ecap))
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clflush_cache_range(pte, sizeof(*pte));
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if (cap_caching_mode(iommu->cap)) {
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pasid_cache_invalidation_with_pasid(iommu, did, pasid);
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qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
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} else {
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iommu_flush_write_buffer(iommu);
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}
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}
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/*
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* Set up the scalable mode pasid table entry for first only
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* translation type.
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*/
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int intel_pasid_setup_first_level(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd,
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u32 pasid, u16 did, int flags)
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{
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struct pasid_entry *pte;
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if (!ecap_flts(iommu->ecap)) {
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pr_err("No first level translation support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) {
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pr_err("No 5-level paging support for first-level on %s\n",
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iommu->name);
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return -EINVAL;
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}
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EBUSY;
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}
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pasid_clear_entry(pte);
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/* Setup the first level page table pointer: */
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pasid_set_flptr(pte, (u64)__pa(pgd));
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if (flags & PASID_FLAG_FL5LP)
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pasid_set_flpm(pte, 1);
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if (flags & PASID_FLAG_PAGE_SNOOP)
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pasid_set_pgsnp(pte);
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pasid_set_domain_id(pte, did);
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pasid_set_address_width(pte, iommu->agaw);
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pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
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/* Setup Present and PASID Granular Transfer Type: */
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pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY);
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pasid_set_present(pte);
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spin_unlock(&iommu->lock);
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pasid_flush_caches(iommu, pte, pasid, did);
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return 0;
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}
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/*
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* Skip top levels of page tables for iommu which has less agaw
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* than default. Unnecessary for PT mode.
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*/
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static int iommu_skip_agaw(struct dmar_domain *domain,
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struct intel_iommu *iommu,
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struct dma_pte **pgd)
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{
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int agaw;
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for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
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*pgd = phys_to_virt(dma_pte_addr(*pgd));
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if (!dma_pte_present(*pgd))
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return -EINVAL;
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}
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return agaw;
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}
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/*
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* Set up the scalable mode pasid entry for second only translation type.
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*/
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int intel_pasid_setup_second_level(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, u32 pasid)
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{
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struct pasid_entry *pte;
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struct dma_pte *pgd;
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u64 pgd_val;
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int agaw;
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u16 did;
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/*
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* If hardware advertises no support for second level
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* translation, return directly.
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*/
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if (!ecap_slts(iommu->ecap)) {
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pr_err("No second level translation support on %s\n",
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iommu->name);
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return -EINVAL;
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}
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pgd = domain->pgd;
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agaw = iommu_skip_agaw(domain, iommu, &pgd);
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if (agaw < 0) {
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dev_err(dev, "Invalid domain page table\n");
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return -EINVAL;
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}
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pgd_val = virt_to_phys(pgd);
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did = domain_id_iommu(domain, iommu);
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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return -ENODEV;
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}
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if (pasid_pte_is_present(pte)) {
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spin_unlock(&iommu->lock);
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return -EBUSY;
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}
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pasid_clear_entry(pte);
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pasid_set_domain_id(pte, did);
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pasid_set_slptr(pte, pgd_val);
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pasid_set_address_width(pte, agaw);
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pasid_set_translation_type(pte, PASID_ENTRY_PGTT_SL_ONLY);
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pasid_set_fault_enable(pte);
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pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
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if (domain->dirty_tracking)
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pasid_set_ssade(pte);
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pasid_set_present(pte);
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spin_unlock(&iommu->lock);
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pasid_flush_caches(iommu, pte, pasid, did);
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return 0;
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}
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/*
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* Set up dirty tracking on a second only or nested translation type.
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*/
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int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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bool enabled)
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{
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struct pasid_entry *pte;
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u16 did, pgtt;
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spin_lock(&iommu->lock);
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pte = intel_pasid_get_entry(dev, pasid);
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if (!pte) {
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spin_unlock(&iommu->lock);
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dev_err_ratelimited(
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dev, "Failed to get pasid entry of PASID %d\n", pasid);
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return -ENODEV;
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}
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did = pasid_get_domain_id(pte);
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pgtt = pasid_pte_get_pgtt(pte);
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if (pgtt != PASID_ENTRY_PGTT_SL_ONLY &&
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pgtt != PASID_ENTRY_PGTT_NESTED) {
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spin_unlock(&iommu->lock);
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dev_err_ratelimited(
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dev,
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"Dirty tracking not supported on translation type %d\n",
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pgtt);
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return -EOPNOTSUPP;
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}
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if (pasid_get_ssade(pte) == enabled) {
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spin_unlock(&iommu->lock);
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return 0;
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}
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if (enabled)
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pasid_set_ssade(pte);
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else
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pasid_clear_ssade(pte);
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spin_unlock(&iommu->lock);
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if (!ecap_coherent(iommu->ecap))
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clflush_cache_range(pte, sizeof(*pte));
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/*
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* From VT-d spec table 25 "Guidance to Software for Invalidations":
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*
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* - PASID-selective-within-Domain PASID-cache invalidation
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* If (PGTT=SS or Nested)
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* - Domain-selective IOTLB invalidation
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* Else
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* - PASID-selective PASID-based IOTLB invalidation
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* - If (pasid is RID_PASID)
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* - Global Device-TLB invalidation to affected functions
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* Else
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* - PASID-based Device-TLB invalidation (with S=1 and
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* Addr[63:12]=0x7FFFFFFF_FFFFF) to affected functions
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*/
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pasid_cache_invalidation_with_pasid(iommu, did, pasid);
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iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
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devtlb_invalidation_with_pasid(iommu, dev, pasid);
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return 0;
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}
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/*
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|
* Set up the scalable mode pasid entry for passthrough translation type.
|
|
*/
|
|
int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
|
|
struct device *dev, u32 pasid)
|
|
{
|
|
u16 did = FLPT_DEFAULT_DID;
|
|
struct pasid_entry *pte;
|
|
|
|
spin_lock(&iommu->lock);
|
|
pte = intel_pasid_get_entry(dev, pasid);
|
|
if (!pte) {
|
|
spin_unlock(&iommu->lock);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pasid_pte_is_present(pte)) {
|
|
spin_unlock(&iommu->lock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
pasid_clear_entry(pte);
|
|
pasid_set_domain_id(pte, did);
|
|
pasid_set_address_width(pte, iommu->agaw);
|
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_PT);
|
|
pasid_set_fault_enable(pte);
|
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
|
|
pasid_set_present(pte);
|
|
spin_unlock(&iommu->lock);
|
|
|
|
pasid_flush_caches(iommu, pte, pasid, did);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set the page snoop control for a pasid entry which has been set up.
|
|
*/
|
|
void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,
|
|
struct device *dev, u32 pasid)
|
|
{
|
|
struct pasid_entry *pte;
|
|
u16 did;
|
|
|
|
spin_lock(&iommu->lock);
|
|
pte = intel_pasid_get_entry(dev, pasid);
|
|
if (WARN_ON(!pte || !pasid_pte_is_present(pte))) {
|
|
spin_unlock(&iommu->lock);
|
|
return;
|
|
}
|
|
|
|
pasid_set_pgsnp(pte);
|
|
did = pasid_get_domain_id(pte);
|
|
spin_unlock(&iommu->lock);
|
|
|
|
if (!ecap_coherent(iommu->ecap))
|
|
clflush_cache_range(pte, sizeof(*pte));
|
|
|
|
/*
|
|
* VT-d spec 3.4 table23 states guides for cache invalidation:
|
|
*
|
|
* - PASID-selective-within-Domain PASID-cache invalidation
|
|
* - PASID-selective PASID-based IOTLB invalidation
|
|
* - If (pasid is RID_PASID)
|
|
* - Global Device-TLB invalidation to affected functions
|
|
* Else
|
|
* - PASID-based Device-TLB invalidation (with S=1 and
|
|
* Addr[63:12]=0x7FFFFFFF_FFFFF) to affected functions
|
|
*/
|
|
pasid_cache_invalidation_with_pasid(iommu, did, pasid);
|
|
qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
|
|
|
|
devtlb_invalidation_with_pasid(iommu, dev, pasid);
|
|
}
|
|
|
|
/**
|
|
* intel_pasid_setup_nested() - Set up PASID entry for nested translation.
|
|
* @iommu: IOMMU which the device belong to
|
|
* @dev: Device to be set up for translation
|
|
* @pasid: PASID to be programmed in the device PASID table
|
|
* @domain: User stage-1 domain nested on a stage-2 domain
|
|
*
|
|
* This is used for nested translation. The input domain should be
|
|
* nested type and nested on a parent with 'is_nested_parent' flag
|
|
* set.
|
|
*/
|
|
int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
|
|
u32 pasid, struct dmar_domain *domain)
|
|
{
|
|
struct iommu_hwpt_vtd_s1 *s1_cfg = &domain->s1_cfg;
|
|
pgd_t *s1_gpgd = (pgd_t *)(uintptr_t)domain->s1_pgtbl;
|
|
struct dmar_domain *s2_domain = domain->s2_domain;
|
|
u16 did = domain_id_iommu(domain, iommu);
|
|
struct dma_pte *pgd = s2_domain->pgd;
|
|
struct pasid_entry *pte;
|
|
|
|
/* Address width should match the address width supported by hardware */
|
|
switch (s1_cfg->addr_width) {
|
|
case ADDR_WIDTH_4LEVEL:
|
|
break;
|
|
case ADDR_WIDTH_5LEVEL:
|
|
if (!cap_fl5lp_support(iommu->cap)) {
|
|
dev_err_ratelimited(dev,
|
|
"5-level paging not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err_ratelimited(dev, "Invalid stage-1 address width %d\n",
|
|
s1_cfg->addr_width);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((s1_cfg->flags & IOMMU_VTD_S1_SRE) && !ecap_srs(iommu->ecap)) {
|
|
pr_err_ratelimited("No supervisor request support on %s\n",
|
|
iommu->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((s1_cfg->flags & IOMMU_VTD_S1_EAFE) && !ecap_eafs(iommu->ecap)) {
|
|
pr_err_ratelimited("No extended access flag support on %s\n",
|
|
iommu->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock(&iommu->lock);
|
|
pte = intel_pasid_get_entry(dev, pasid);
|
|
if (!pte) {
|
|
spin_unlock(&iommu->lock);
|
|
return -ENODEV;
|
|
}
|
|
if (pasid_pte_is_present(pte)) {
|
|
spin_unlock(&iommu->lock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
pasid_clear_entry(pte);
|
|
|
|
if (s1_cfg->addr_width == ADDR_WIDTH_5LEVEL)
|
|
pasid_set_flpm(pte, 1);
|
|
|
|
pasid_set_flptr(pte, (uintptr_t)s1_gpgd);
|
|
|
|
if (s1_cfg->flags & IOMMU_VTD_S1_SRE) {
|
|
pasid_set_sre(pte);
|
|
if (s1_cfg->flags & IOMMU_VTD_S1_WPE)
|
|
pasid_set_wpe(pte);
|
|
}
|
|
|
|
if (s1_cfg->flags & IOMMU_VTD_S1_EAFE)
|
|
pasid_set_eafe(pte);
|
|
|
|
if (s2_domain->force_snooping)
|
|
pasid_set_pgsnp(pte);
|
|
|
|
pasid_set_slptr(pte, virt_to_phys(pgd));
|
|
pasid_set_fault_enable(pte);
|
|
pasid_set_domain_id(pte, did);
|
|
pasid_set_address_width(pte, s2_domain->agaw);
|
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
|
|
if (s2_domain->dirty_tracking)
|
|
pasid_set_ssade(pte);
|
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_NESTED);
|
|
pasid_set_present(pte);
|
|
spin_unlock(&iommu->lock);
|
|
|
|
pasid_flush_caches(iommu, pte, pasid, did);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Interfaces to setup or teardown a pasid table to the scalable-mode
|
|
* context table entry:
|
|
*/
|
|
|
|
static void device_pasid_table_teardown(struct device *dev, u8 bus, u8 devfn)
|
|
{
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
|
struct intel_iommu *iommu = info->iommu;
|
|
struct context_entry *context;
|
|
u16 did;
|
|
|
|
spin_lock(&iommu->lock);
|
|
context = iommu_context_addr(iommu, bus, devfn, false);
|
|
if (!context) {
|
|
spin_unlock(&iommu->lock);
|
|
return;
|
|
}
|
|
|
|
did = context_domain_id(context);
|
|
context_clear_entry(context);
|
|
__iommu_flush_cache(iommu, context, sizeof(*context));
|
|
spin_unlock(&iommu->lock);
|
|
intel_context_flush_present(info, context, did, false);
|
|
}
|
|
|
|
static int pci_pasid_table_teardown(struct pci_dev *pdev, u16 alias, void *data)
|
|
{
|
|
struct device *dev = data;
|
|
|
|
if (dev == &pdev->dev)
|
|
device_pasid_table_teardown(dev, PCI_BUS_NUM(alias), alias & 0xff);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void intel_pasid_teardown_sm_context(struct device *dev)
|
|
{
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
|
|
|
if (!dev_is_pci(dev)) {
|
|
device_pasid_table_teardown(dev, info->bus, info->devfn);
|
|
return;
|
|
}
|
|
|
|
pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_teardown, dev);
|
|
}
|
|
|
|
/*
|
|
* Get the PASID directory size for scalable mode context entry.
|
|
* Value of X in the PDTS field of a scalable mode context entry
|
|
* indicates PASID directory with 2^(X + 7) entries.
|
|
*/
|
|
static unsigned long context_get_sm_pds(struct pasid_table *table)
|
|
{
|
|
unsigned long pds, max_pde;
|
|
|
|
max_pde = table->max_pasid >> PASID_PDE_SHIFT;
|
|
pds = find_first_bit(&max_pde, MAX_NR_PASID_BITS);
|
|
if (pds < 7)
|
|
return 0;
|
|
|
|
return pds - 7;
|
|
}
|
|
|
|
static int context_entry_set_pasid_table(struct context_entry *context,
|
|
struct device *dev)
|
|
{
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
|
struct pasid_table *table = info->pasid_table;
|
|
struct intel_iommu *iommu = info->iommu;
|
|
unsigned long pds;
|
|
|
|
context_clear_entry(context);
|
|
|
|
pds = context_get_sm_pds(table);
|
|
context->lo = (u64)virt_to_phys(table->table) | context_pdts(pds);
|
|
context_set_sm_rid2pasid(context, IOMMU_NO_PASID);
|
|
|
|
if (info->ats_supported)
|
|
context_set_sm_dte(context);
|
|
if (info->pasid_supported)
|
|
context_set_pasid(context);
|
|
|
|
context_set_fault_enable(context);
|
|
context_set_present(context);
|
|
__iommu_flush_cache(iommu, context, sizeof(*context));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int device_pasid_table_setup(struct device *dev, u8 bus, u8 devfn)
|
|
{
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
|
struct intel_iommu *iommu = info->iommu;
|
|
struct context_entry *context;
|
|
|
|
spin_lock(&iommu->lock);
|
|
context = iommu_context_addr(iommu, bus, devfn, true);
|
|
if (!context) {
|
|
spin_unlock(&iommu->lock);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (context_present(context) && !context_copied(iommu, bus, devfn)) {
|
|
spin_unlock(&iommu->lock);
|
|
return 0;
|
|
}
|
|
|
|
if (context_copied(iommu, bus, devfn)) {
|
|
context_clear_entry(context);
|
|
__iommu_flush_cache(iommu, context, sizeof(*context));
|
|
|
|
/*
|
|
* For kdump cases, old valid entries may be cached due to
|
|
* the in-flight DMA and copied pgtable, but there is no
|
|
* unmapping behaviour for them, thus we need explicit cache
|
|
* flushes for all affected domain IDs and PASIDs used in
|
|
* the copied PASID table. Given that we have no idea about
|
|
* which domain IDs and PASIDs were used in the copied tables,
|
|
* upgrade them to global PASID and IOTLB cache invalidation.
|
|
*/
|
|
iommu->flush.flush_context(iommu, 0,
|
|
PCI_DEVID(bus, devfn),
|
|
DMA_CCMD_MASK_NOBIT,
|
|
DMA_CCMD_DEVICE_INVL);
|
|
qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
|
|
devtlb_invalidation_with_pasid(iommu, dev, IOMMU_NO_PASID);
|
|
|
|
/*
|
|
* At this point, the device is supposed to finish reset at
|
|
* its driver probe stage, so no in-flight DMA will exist,
|
|
* and we don't need to worry anymore hereafter.
|
|
*/
|
|
clear_context_copied(iommu, bus, devfn);
|
|
}
|
|
|
|
context_entry_set_pasid_table(context, dev);
|
|
spin_unlock(&iommu->lock);
|
|
|
|
/*
|
|
* It's a non-present to present mapping. If hardware doesn't cache
|
|
* non-present entry we don't need to flush the caches. If it does
|
|
* cache non-present entries, then it does so in the special
|
|
* domain #0, which we have to flush:
|
|
*/
|
|
if (cap_caching_mode(iommu->cap)) {
|
|
iommu->flush.flush_context(iommu, 0,
|
|
PCI_DEVID(bus, devfn),
|
|
DMA_CCMD_MASK_NOBIT,
|
|
DMA_CCMD_DEVICE_INVL);
|
|
iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_pasid_table_setup(struct pci_dev *pdev, u16 alias, void *data)
|
|
{
|
|
struct device *dev = data;
|
|
|
|
if (dev != &pdev->dev)
|
|
return 0;
|
|
|
|
return device_pasid_table_setup(dev, PCI_BUS_NUM(alias), alias & 0xff);
|
|
}
|
|
|
|
/*
|
|
* Set the device's PASID table to its context table entry.
|
|
*
|
|
* The PASID table is set to the context entries of both device itself
|
|
* and its alias requester ID for DMA.
|
|
*/
|
|
int intel_pasid_setup_sm_context(struct device *dev)
|
|
{
|
|
struct device_domain_info *info = dev_iommu_priv_get(dev);
|
|
|
|
if (!dev_is_pci(dev))
|
|
return device_pasid_table_setup(dev, info->bus, info->devfn);
|
|
|
|
return pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_setup, dev);
|
|
}
|
|
|
|
/*
|
|
* Global Device-TLB invalidation following changes in a context entry which
|
|
* was present.
|
|
*/
|
|
static void __context_flush_dev_iotlb(struct device_domain_info *info)
|
|
{
|
|
if (!info->ats_enabled)
|
|
return;
|
|
|
|
qi_flush_dev_iotlb(info->iommu, PCI_DEVID(info->bus, info->devfn),
|
|
info->pfsid, info->ats_qdep, 0, MAX_AGAW_PFN_WIDTH);
|
|
|
|
/*
|
|
* There is no guarantee that the device DMA is stopped when it reaches
|
|
* here. Therefore, always attempt the extra device TLB invalidation
|
|
* quirk. The impact on performance is acceptable since this is not a
|
|
* performance-critical path.
|
|
*/
|
|
quirk_extra_dev_tlb_flush(info, 0, MAX_AGAW_PFN_WIDTH, IOMMU_NO_PASID,
|
|
info->ats_qdep);
|
|
}
|
|
|
|
/*
|
|
* Cache invalidations after change in a context table entry that was present
|
|
* according to the Spec 6.5.3.3 (Guidance to Software for Invalidations). If
|
|
* IOMMU is in scalable mode and all PASID table entries of the device were
|
|
* non-present, set flush_domains to false. Otherwise, true.
|
|
*/
|
|
void intel_context_flush_present(struct device_domain_info *info,
|
|
struct context_entry *context,
|
|
u16 did, bool flush_domains)
|
|
{
|
|
struct intel_iommu *iommu = info->iommu;
|
|
struct pasid_entry *pte;
|
|
int i;
|
|
|
|
/*
|
|
* Device-selective context-cache invalidation. The Domain-ID field
|
|
* of the Context-cache Invalidate Descriptor is ignored by hardware
|
|
* when operating in scalable mode. Therefore the @did value doesn't
|
|
* matter in scalable mode.
|
|
*/
|
|
iommu->flush.flush_context(iommu, did, PCI_DEVID(info->bus, info->devfn),
|
|
DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL);
|
|
|
|
/*
|
|
* For legacy mode:
|
|
* - Domain-selective IOTLB invalidation
|
|
* - Global Device-TLB invalidation to all affected functions
|
|
*/
|
|
if (!sm_supported(iommu)) {
|
|
iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
|
|
__context_flush_dev_iotlb(info);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* For scalable mode:
|
|
* - Domain-selective PASID-cache invalidation to affected domains
|
|
* - Domain-selective IOTLB invalidation to affected domains
|
|
* - Global Device-TLB invalidation to affected functions
|
|
*/
|
|
if (flush_domains) {
|
|
/*
|
|
* If the IOMMU is running in scalable mode and there might
|
|
* be potential PASID translations, the caller should hold
|
|
* the lock to ensure that context changes and cache flushes
|
|
* are atomic.
|
|
*/
|
|
assert_spin_locked(&iommu->lock);
|
|
for (i = 0; i < info->pasid_table->max_pasid; i++) {
|
|
pte = intel_pasid_get_entry(info->dev, i);
|
|
if (!pte || !pasid_pte_is_present(pte))
|
|
continue;
|
|
|
|
did = pasid_get_domain_id(pte);
|
|
qi_flush_pasid_cache(iommu, did, QI_PC_ALL_PASIDS, 0);
|
|
iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
|
|
}
|
|
}
|
|
|
|
__context_flush_dev_iotlb(info);
|
|
}
|