From 93c60483b5feefced92b869d5f97769495bc6313 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 9 Dec 2019 13:55:15 -0800 Subject: bus: ti-sysc: Fix missing force mstandby quirk handling Commit 03856e928b0e ("bus: ti-sysc: Handle mstandby quirk and use it for musb") added quirk handling for mstandby quirk but did not consider that we also need a quirk variant for SYSC_QUIRK_FORCE_MSTANDBY. We need to use forced idle mode for both SYSC_QUIRK_SWSUP_MSTANDBY and SYSC_QUIRK_FORCE_MSTANDBY, but SYSC_QUIRK_SWSUP_MSTANDBY also need to additionally also configure no-idle mode when enabled. Fixes: 03856e928b0e ("bus: ti-sysc: Handle mstandby quirk and use it for musb") Signed-off-by: Tony Lindgren --- include/linux/platform_data/ti-sysc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 0b9380475144..8cfe570fdece 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -49,6 +49,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20) #define SYSC_MODULE_QUIRK_AESS BIT(19) #define SYSC_MODULE_QUIRK_SGX BIT(18) #define SYSC_MODULE_QUIRK_HDQ1W BIT(17) -- cgit From 28b5afcd06d2b24e31ca4a643ddee9eb92b5bcb1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Drop unused sdma functions We still have lots of legacy code for sdma, but some of it is now unused. To simplify phasing out the old legacy sdma code, let's first remove all currently unused functions: omap_enable_dma_irq omap_set_dma_write_mode omap_set_dma_params omap_dma_link_lch omap_set_dma_callback omap_dma_set_global_params And with this, omap_dma_set_global_params now becomes static. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 149 +---------------------------------------------- include/linux/omap-dma.h | 12 ---- 2 files changed, 1 insertion(+), 160 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 08c99413d02c..8f441f125ce1 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -65,8 +65,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; static struct omap_system_dma_plat_info *p; static struct omap_dma_dev_attr *d; static void omap_clear_dma(int lch); -static int omap_dma_set_prio_lch(int lch, unsigned char read_prio, - unsigned char write_prio); static int enable_1510_mode; static u32 errata; @@ -95,20 +93,6 @@ static struct dma_link_info *dma_linked_lch; #ifndef CONFIG_ARCH_OMAP1 /* Chain handling macros */ -#define OMAP_DMA_CHAIN_QINIT(chain_id) \ - do { \ - dma_linked_lch[chain_id].q_head = \ - dma_linked_lch[chain_id].q_tail = \ - dma_linked_lch[chain_id].q_count = 0; \ - } while (0) -#define OMAP_DMA_CHAIN_QFULL(chain_id) \ - (dma_linked_lch[chain_id].no_of_lchs_linked == \ - dma_linked_lch[chain_id].q_count) -#define OMAP_DMA_CHAIN_QLAST(chain_id) \ - do { \ - ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ - dma_linked_lch[chain_id].q_count) \ - } while (0) #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ (0 == dma_linked_lch[chain_id].q_count) #define __OMAP_DMA_CHAIN_INCQ(end) \ @@ -118,12 +102,6 @@ static struct dma_link_info *dma_linked_lch; __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ dma_linked_lch[chain_id].q_count--; \ } while (0) - -#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ - dma_linked_lch[chain_id].q_count++; \ - } while (0) #endif static int dma_lch_count; @@ -137,9 +115,6 @@ static inline void disable_lnk(int lch); static void omap_disable_channel_irq(int lch); static inline void omap_enable_channel_irq(int lch); -#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ - __func__); - #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ static int omap_dma_in_1510_mode(void) @@ -278,19 +253,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, } EXPORT_SYMBOL(omap_set_dma_transfer_params); -void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) -{ - if (dma_omap2plus()) { - u32 csdp; - - csdp = p->dma_read(CSDP, lch); - csdp &= ~(0x3 << 16); - csdp |= (mode << 16); - p->dma_write(csdp, CSDP, lch); - } -} -EXPORT_SYMBOL(omap_set_dma_write_mode); - void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) { if (dma_omap1() && !dma_omap15xx()) { @@ -332,25 +294,6 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, } EXPORT_SYMBOL(omap_set_dma_src_params); -void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) -{ - omap_set_dma_transfer_params(lch, params->data_type, - params->elem_count, params->frame_count, - params->sync_mode, params->trigger, - params->src_or_dst_synch); - omap_set_dma_src_params(lch, params->src_port, - params->src_amode, params->src_start, - params->src_ei, params->src_fi); - - omap_set_dma_dest_params(lch, params->dst_port, - params->dst_amode, params->dst_start, - params->dst_ei, params->dst_fi); - if (params->read_prio || params->write_prio) - omap_dma_set_prio_lch(lch, params->read_prio, - params->write_prio); -} -EXPORT_SYMBOL(omap_set_dma_params); - void omap_set_dma_src_data_pack(int lch, int enable) { u32 l; @@ -507,12 +450,6 @@ static inline void omap_disable_channel_irq(int lch) p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); } -void omap_enable_dma_irq(int lch, u16 bits) -{ - dma_chan[lch].enabled_irqs |= bits; -} -EXPORT_SYMBOL(omap_enable_dma_irq); - void omap_disable_dma_irq(int lch, u16 bits) { dma_chan[lch].enabled_irqs &= ~bits; @@ -721,7 +658,7 @@ EXPORT_SYMBOL(omap_free_dma); * DMA_THREAD_RESERVE_TWOT * DMA_THREAD_RESERVE_THREET */ -void +static void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) { u32 reg; @@ -742,39 +679,6 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) p->dma_write(reg, GCR, 0); } -EXPORT_SYMBOL(omap_dma_set_global_params); - -/** - * @brief omap_dma_set_prio_lch : Set channel wise priority settings - * - * @param lch - * @param read_prio - Read priority - * @param write_prio - Write priority - * Both of the above can be set with one of the following values : - * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW - */ -static int -omap_dma_set_prio_lch(int lch, unsigned char read_prio, - unsigned char write_prio) -{ - u32 l; - - if (unlikely((lch < 0 || lch >= dma_lch_count))) { - printk(KERN_ERR "Invalid channel id\n"); - return -EINVAL; - } - l = p->dma_read(CCR, lch); - l &= ~((1 << 6) | (1 << 26)); - if (d->dev_caps & IS_RW_PRIORITY) - l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); - else - l |= ((read_prio & 0x1) << 6); - - p->dma_write(l, CCR, lch); - - return 0; -} - /* * Clears any DMA state so the DMA engine is ready to restart with new buffers @@ -926,29 +830,6 @@ EXPORT_SYMBOL(omap_stop_dma); * Allows changing the DMA callback function or data. This may be needed if * the driver shares a single DMA channel for multiple dma triggers. */ -int omap_set_dma_callback(int lch, - void (*callback)(int lch, u16 ch_status, void *data), - void *data) -{ - unsigned long flags; - - if (lch < 0) - return -ENODEV; - - spin_lock_irqsave(&dma_chan_lock, flags); - if (dma_chan[lch].dev_id == -1) { - printk(KERN_ERR "DMA callback for not set for free channel\n"); - spin_unlock_irqrestore(&dma_chan_lock, flags); - return -EINVAL; - } - dma_chan[lch].callback = callback; - dma_chan[lch].data = data; - spin_unlock_irqrestore(&dma_chan_lock, flags); - - return 0; -} -EXPORT_SYMBOL(omap_set_dma_callback); - /* * Returns current physical source address for the given DMA channel. * If the channel is running the caller must disable interrupts prior calling @@ -1048,34 +929,6 @@ int omap_dma_running(void) return 0; } -/* - * lch_queue DMA will start right after lch_head one is finished. - * For this DMA link to start, you still need to start (see omap_start_dma) - * the first one. That will fire up the entire queue. - */ -void omap_dma_link_lch(int lch_head, int lch_queue) -{ - if (omap_dma_in_1510_mode()) { - if (lch_head == lch_queue) { - p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), - CCR, lch_head); - return; - } - printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); - BUG(); - return; - } - - if ((dma_chan[lch_head].dev_id == -1) || - (dma_chan[lch_queue].dev_id == -1)) { - pr_err("omap_dma: trying to link non requested channels\n"); - dump_stack(); - } - - dma_chan[lch_head].next_lch = lch_queue; -} -EXPORT_SYMBOL(omap_dma_link_lch); - /*----------------------------------------------------------------------------*/ #ifdef CONFIG_ARCH_OMAP1 diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index ba3cfbb52312..61e474ce3ccb 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -303,7 +303,6 @@ extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch); -extern void omap_enable_dma_irq(int ch, u16 irq_bits); extern void omap_disable_dma_irq(int ch, u16 irq_bits); extern void omap_free_dma(int ch); extern void omap_start_dma(int lch); @@ -312,7 +311,6 @@ extern void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, int frame_count, int sync_mode, int dma_trigger, int src_or_dst_synch); -extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, @@ -329,20 +327,10 @@ extern void omap_set_dma_dest_data_pack(int lch, int enable); extern void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode); -extern void omap_set_dma_params(int lch, - struct omap_dma_channel_params *params); - -extern void omap_dma_link_lch(int lch_head, int lch_queue); - -extern int omap_set_dma_callback(int lch, - void (*callback)(int lch, u16 ch_status, void *data), - void *data); extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); extern int omap_get_dma_active_status(int lch); extern int omap_dma_running(void); -extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, - int tparams); void omap_dma_global_context_save(void); void omap_dma_global_context_restore(void); -- cgit From 755cbfd8cf89c09e53be796d7d5c22f2d197ef1a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: ARM: OMAP2+: Drop sdma interrupt handling for mach-omap2 All device tree probing omap SoCs only have device drivers that are using Linux dmaengine API with the IRQENABLE_L1 interrupts. Only omap1 is still using old legacy dma. This means we can remove the legacy sdma interrupt handling for IRQENABLE_L0, and only rely on the dmaengine driver using IRQENABLE_L1. The legacy code still allocates the channels, but that will be deal with in the following patches. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/dma.c | 3 - arch/arm/plat-omap/dma.c | 245 ++-------------------------------------------- include/linux/omap-dma.h | 4 - 3 files changed, 8 insertions(+), 244 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 0c105baa5e88..c138703aab90 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -272,9 +272,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) d->dev_caps |= HS_CHANNELS_RESERVED; - if (platform_get_irq_byname(pdev, "0") < 0) - d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; - /* Check the capabilities register for descriptor loading feature */ if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) dma_common_ch_end = CCDN; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 8f441f125ce1..8aea155b10a8 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -88,22 +88,6 @@ struct dma_link_info { }; -static struct dma_link_info *dma_linked_lch; - -#ifndef CONFIG_ARCH_OMAP1 - -/* Chain handling macros */ -#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ - (0 == dma_linked_lch[chain_id].q_count) -#define __OMAP_DMA_CHAIN_INCQ(end) \ - ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) -#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ - do { \ - __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ - dma_linked_lch[chain_id].q_count--; \ - } while (0) -#endif - static int dma_lch_count; static int dma_chan_count; static int omap_dma_reserve_channels; @@ -469,12 +453,6 @@ static inline void enable_lnk(int lch) if (dma_chan[lch].next_lch != -1) l = dma_chan[lch].next_lch | (1 << 15); -#ifndef CONFIG_ARCH_OMAP1 - if (dma_omap2plus()) - if (dma_chan[lch].next_linked_ch != -1) - l = dma_chan[lch].next_linked_ch | (1 << 15); -#endif - p->dma_write(l, CLNK_CTRL, lch); } @@ -501,42 +479,6 @@ static inline void disable_lnk(int lch) dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } -static inline void omap2_enable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (dma_omap1()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - /* clear IRQ STATUS */ - p->dma_write(1 << lch, IRQSTATUS_L0, lch); - /* Enable interrupt */ - val = p->dma_read(IRQENABLE_L0, lch); - val |= 1 << lch; - p->dma_write(val, IRQENABLE_L0, lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - -static inline void omap2_disable_irq_lch(int lch) -{ - u32 val; - unsigned long flags; - - if (dma_omap1()) - return; - - spin_lock_irqsave(&dma_chan_lock, flags); - /* Disable interrupt */ - val = p->dma_read(IRQENABLE_L0, lch); - val &= ~(1 << lch); - p->dma_write(val, IRQENABLE_L0, lch); - /* clear IRQ STATUS */ - p->dma_write(1 << lch, IRQSTATUS_L0, lch); - spin_unlock_irqrestore(&dma_chan_lock, flags); -} - int omap_request_dma(int dev_id, const char *dev_name, void (*callback)(int lch, u16 ch_status, void *data), void *data, int *dma_ch_out) @@ -565,9 +507,6 @@ int omap_request_dma(int dev_id, const char *dev_name, if (p->clear_lch_regs) p->clear_lch_regs(free_ch); - if (dma_omap2plus()) - omap_clear_dma(free_ch); - spin_unlock_irqrestore(&dma_chan_lock, flags); chan->dev_name = dev_name; @@ -575,20 +514,10 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->data = data; chan->flags = 0; -#ifndef CONFIG_ARCH_OMAP1 - if (dma_omap2plus()) { - chan->chain_id = -1; - chan->next_linked_ch = -1; - } -#endif - chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; if (dma_omap1()) chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; - else if (dma_omap2plus()) - chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | - OMAP2_DMA_TRANS_ERR_IRQ; if (dma_omap16xx()) { /* If the sync device is set, configure it dynamically. */ @@ -605,11 +534,6 @@ int omap_request_dma(int dev_id, const char *dev_name, p->dma_write(dev_id, CCR, free_ch); } - if (dma_omap2plus()) { - omap_enable_channel_irq(free_ch); - omap2_enable_irq_lch(free_ch); - } - *dma_ch_out = free_ch; return 0; @@ -626,20 +550,12 @@ void omap_free_dma(int lch) return; } - /* Disable interrupt for logical channel */ - if (dma_omap2plus()) - omap2_disable_irq_lch(lch); - /* Disable all DMA interrupts for the channel. */ omap_disable_channel_irq(lch); /* Make sure the DMA transfer is stopped. */ p->dma_write(0, CCR, lch); - /* Clear registers */ - if (dma_omap2plus()) - omap_clear_dma(lch); - spin_lock_irqsave(&dma_chan_lock, flags); dma_chan[lch].dev_id = -1; dma_chan[lch].next_lch = -1; @@ -989,109 +905,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -#ifdef CONFIG_ARCH_OMAP2PLUS - -static int omap2_dma_handle_ch(int ch) -{ - u32 status = p->dma_read(CSR, ch); - - if (!status) { - if (printk_ratelimit()) - pr_warn("Spurious DMA IRQ for lch %d\n", ch); - p->dma_write(1 << ch, IRQSTATUS_L0, ch); - return 0; - } - if (unlikely(dma_chan[ch].dev_id == -1)) { - if (printk_ratelimit()) - pr_warn("IRQ %04x for non-allocated DMA channel %d\n", - status, ch); - return 0; - } - if (unlikely(status & OMAP_DMA_DROP_IRQ)) - pr_info("DMA synchronization event drop occurred with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { - printk(KERN_INFO "DMA transaction error with device %d\n", - dma_chan[ch].dev_id); - if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { - u32 ccr; - - ccr = p->dma_read(CCR, ch); - ccr &= ~OMAP_DMA_CCR_EN; - p->dma_write(ccr, CCR, ch); - dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; - } - } - if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) - printk(KERN_INFO "DMA secure error with device %d\n", - dma_chan[ch].dev_id); - if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) - printk(KERN_INFO "DMA misaligned error with device %d\n", - dma_chan[ch].dev_id); - - p->dma_write(status, CSR, ch); - p->dma_write(1 << ch, IRQSTATUS_L0, ch); - /* read back the register to flush the write */ - p->dma_read(IRQSTATUS_L0, ch); - - /* If the ch is not chained then chain_id will be -1 */ - if (dma_chan[ch].chain_id != -1) { - int chain_id = dma_chan[ch].chain_id; - dma_chan[ch].state = DMA_CH_NOTSTARTED; - if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) - dma_chan[dma_chan[ch].next_linked_ch].state = - DMA_CH_STARTED; - if (dma_linked_lch[chain_id].chain_mode == - OMAP_DMA_DYNAMIC_CHAIN) - disable_lnk(ch); - - if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) - OMAP_DMA_CHAIN_INCQHEAD(chain_id); - - status = p->dma_read(CSR, ch); - p->dma_write(status, CSR, ch); - } - - if (likely(dma_chan[ch].callback != NULL)) - dma_chan[ch].callback(ch, status, dma_chan[ch].data); - - return 0; -} - -/* STATUS register count is from 1-32 while our is 0-31 */ -static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) -{ - u32 val, enable_reg; - int i; - - val = p->dma_read(IRQSTATUS_L0, 0); - if (val == 0) { - if (printk_ratelimit()) - printk(KERN_WARNING "Spurious DMA IRQ\n"); - return IRQ_HANDLED; - } - enable_reg = p->dma_read(IRQENABLE_L0, 0); - val &= enable_reg; /* Dispatch only relevant interrupts */ - for (i = 0; i < dma_lch_count && val != 0; i++) { - if (val & 1) - omap2_dma_handle_ch(i); - val >>= 1; - } - - return IRQ_HANDLED; -} - -static struct irqaction omap24xx_dma_irq = { - .name = "DMA", - .handler = omap2_dma_irq_handler, -}; - -#else -static struct irqaction omap24xx_dma_irq; -#endif - -/*----------------------------------------------------------------------------*/ - /* * Note that we are currently using only IRQENABLE_L0 and L1. * As the DSP may be using IRQENABLE_L2 and L3, let's not @@ -1139,7 +952,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) int ch, ret = 0; int dma_irq; char irq_name[4]; - int irq_rel; p = pdev->dev.platform_data; if (!p) { @@ -1165,21 +977,9 @@ static int omap_system_dma_probe(struct platform_device *pdev) if (!dma_chan) return -ENOMEM; - if (dma_omap2plus()) { - dma_linked_lch = kcalloc(dma_lch_count, - sizeof(*dma_linked_lch), - GFP_KERNEL); - if (!dma_linked_lch) { - ret = -ENOMEM; - goto exit_dma_lch_fail; - } - } - spin_lock_init(&dma_chan_lock); for (ch = 0; ch < dma_chan_count; ch++) { omap_clear_dma(ch); - if (dma_omap2plus()) - omap2_disable_irq_lch(ch); dma_chan[ch].dev_id = -1; dma_chan[ch].next_lch = -1; @@ -1216,22 +1016,6 @@ static int omap_system_dma_probe(struct platform_device *pdev) omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0); - if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) { - strcpy(irq_name, "0"); - dma_irq = platform_get_irq_byname(pdev, irq_name); - if (dma_irq < 0) { - dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); - ret = dma_irq; - goto exit_dma_lch_fail; - } - ret = setup_irq(dma_irq, &omap24xx_dma_irq); - if (ret) { - dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", - dma_irq, ret); - goto exit_dma_lch_fail; - } - } - /* reserve dma channels 0 and 1 in high security devices on 34xx */ if (d->dev_caps & HS_CHANNELS_RESERVED) { pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); @@ -1242,34 +1026,21 @@ static int omap_system_dma_probe(struct platform_device *pdev) return 0; exit_dma_irq_fail: - dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", - dma_irq, ret); - for (irq_rel = 0; irq_rel < ch; irq_rel++) { - dma_irq = platform_get_irq(pdev, irq_rel); - free_irq(dma_irq, (void *)(irq_rel + 1)); - } - -exit_dma_lch_fail: return ret; } static int omap_system_dma_remove(struct platform_device *pdev) { - int dma_irq; + int dma_irq, irq_rel = 0; - if (dma_omap2plus()) { - char irq_name[4]; - strcpy(irq_name, "0"); - dma_irq = platform_get_irq_byname(pdev, irq_name); - if (dma_irq >= 0) - remove_irq(dma_irq, &omap24xx_dma_irq); - } else { - int irq_rel = 0; - for ( ; irq_rel < dma_chan_count; irq_rel++) { - dma_irq = platform_get_irq(pdev, irq_rel); - free_irq(dma_irq, (void *)(irq_rel + 1)); - } + if (dma_omap2plus()) + return 0; + + for ( ; irq_rel < dma_chan_count; irq_rel++) { + dma_irq = platform_get_irq(pdev, irq_rel); + free_irq(dma_irq, (void *)(irq_rel + 1)); } + return 0; } diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index 61e474ce3ccb..ee0de8443274 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -129,7 +129,6 @@ #define IS_WORD_16 BIT(0xd) #define ENABLE_16XX_MODE BIT(0xe) #define HS_CHANNELS_RESERVED BIT(0xf) -#define DMA_ENGINE_HANDLE_IRQ BIT(0x10) /* Defines for DMA Capabilities */ #define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) @@ -239,9 +238,6 @@ struct omap_dma_lch { void (*callback)(int lch, u16 ch_status, void *data); void *data; long flags; - /* required for Dynamic chaining */ - int prev_linked_ch; - int next_linked_ch; int state; int chain_id; int status; -- cgit From 4c74ecf79227228f31d05d6d4766ccb5f8607b83 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Dec 2019 14:41:53 -0800 Subject: dmaengine: ti: omap-dma: Add device tree match data and use it for cpu_pm With old DMA code disabled for handling DMA requests for device tree based SoCs, we can move omap3 specific context save and restore to the dmaengine driver. Let's do this by adding cpu_pm notifier handling to save and restore context, and enable it based on device tree match data. This way we can use the match data later to configure more SoC specific features later on too. Note that we only clear the channels in use while the platform code also clears reserved channels 0 and 1 on high-security SoCs. Based on testing on n900, this is not needed though and the system idles just fine. With the dmaengine driver handling context save and restore, we must now remove the old custom calls for context save and restore. Cc: Aaro Koskinen Cc: Arnd Bergmann Cc: Peter Ujfalusi Cc: Russell King Cc: Vinod Koul Acked-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Acked-by: Vinod Koul Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 5 -- arch/arm/plat-omap/dma.c | 43 ------------- drivers/dma/ti/omap-dma.c | 150 +++++++++++++++++++++++++++++++++++++++---- include/linux/omap-dma.h | 2 - 4 files changed, 138 insertions(+), 62 deletions(-) (limited to 'include/linux') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 54254fc92c2e..e66e9948636c 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -85,7 +84,6 @@ static void omap3_core_save_context(void) omap3_gpmc_save_context(); /* Save the system control module context, padconf already save above*/ omap3_control_save_context(); - omap_dma_global_context_save(); } static void omap3_core_restore_context(void) @@ -96,7 +94,6 @@ static void omap3_core_restore_context(void) omap3_gpmc_restore_context(); /* Restore the interrupt controller context */ omap_intc_restore_context(); - omap_dma_global_context_restore(); } /* @@ -547,9 +544,7 @@ int __init omap3_pm_init(void) local_irq_disable(); - omap_dma_global_context_save(); omap3_save_secure_ram_context(); - omap_dma_global_context_restore(); local_irq_enable(); } diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 8aea155b10a8..0f68c6faecad 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -68,13 +68,6 @@ static void omap_clear_dma(int lch); static int enable_1510_mode; static u32 errata; -static struct omap_dma_global_context_registers { - u32 dma_irqenable_l0; - u32 dma_irqenable_l1; - u32 dma_ocp_sysconfig; - u32 dma_gcr; -} omap_dma_global_context; - struct dma_link_info { int *linked_dmach_q; int no_of_lchs_linked; @@ -905,42 +898,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) #define omap1_dma_irq_handler NULL #endif -/* - * Note that we are currently using only IRQENABLE_L0 and L1. - * As the DSP may be using IRQENABLE_L2 and L3, let's not - * touch those for now. - */ -void omap_dma_global_context_save(void) -{ - omap_dma_global_context.dma_irqenable_l0 = - p->dma_read(IRQENABLE_L0, 0); - omap_dma_global_context.dma_irqenable_l1 = - p->dma_read(IRQENABLE_L1, 0); - omap_dma_global_context.dma_ocp_sysconfig = - p->dma_read(OCP_SYSCONFIG, 0); - omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); -} - -void omap_dma_global_context_restore(void) -{ - int ch; - - p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); - p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, - OCP_SYSCONFIG, 0); - p->dma_write(omap_dma_global_context.dma_irqenable_l0, - IRQENABLE_L0, 0); - p->dma_write(omap_dma_global_context.dma_irqenable_l1, - IRQENABLE_L1, 0); - - if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) - p->dma_write(0x3 , IRQSTATUS_L0, 0); - - for (ch = 0; ch < dma_chan_count; ch++) - if (dma_chan[ch].dev_id != -1) - omap_clear_dma(ch); -} - struct omap_system_dma_plat_info *omap_get_plat_info(void) { return p; diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c index 6b6ba238b81a..5423cb7b5256 100644 --- a/drivers/dma/ti/omap-dma.c +++ b/drivers/dma/ti/omap-dma.c @@ -2,6 +2,7 @@ /* * OMAP DMAengine support */ +#include #include #include #include @@ -23,12 +24,28 @@ #define OMAP_SDMA_REQUESTS 127 #define OMAP_SDMA_CHANNELS 32 +struct omap_dma_config { + int lch_end; + unsigned int may_lose_context:1; +}; + +struct omap_dma_context { + u32 irqenable_l0; + u32 irqenable_l1; + u32 ocp_sysconfig; + u32 gcr; +}; + struct omap_dmadev { struct dma_device ddev; spinlock_t lock; void __iomem *base; const struct omap_dma_reg *reg_map; struct omap_system_dma_plat_info *plat; + const struct omap_dma_config *cfg; + struct notifier_block nb; + struct omap_dma_context context; + int lch_count; bool legacy; bool ll123_supported; struct dma_pool *desc_pool; @@ -376,6 +393,19 @@ static unsigned omap_dma_get_csr(struct omap_chan *c) return val; } +static void omap_dma_clear_lch(struct omap_dmadev *od, int lch) +{ + struct omap_chan *c; + int i; + + c = od->lch_map[lch]; + if (!c) + return; + + for (i = CSDP; i <= od->cfg->lch_end; i++) + omap_dma_chan_write(c, i, 0); +} + static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, unsigned lch) { @@ -652,6 +682,7 @@ static int omap_dma_alloc_chan_resources(struct dma_chan *chan) if (ret >= 0) { omap_dma_assign(od, c, c->dma_ch); + pr_info("XXX %s: assigned lch: %i\n", __func__, c->dma_ch); if (!od->legacy) { unsigned val; @@ -1453,16 +1484,74 @@ static void omap_dma_free(struct omap_dmadev *od) } } +/* + * We are using IRQENABLE_L1, and legacy DMA code was using IRQENABLE_L0. + * As the DSP may be using IRQENABLE_L2 and L3, let's not touch those for + * now. Context save seems to be only currently needed on omap3. + */ +static void omap_dma_context_save(struct omap_dmadev *od) +{ + od->context.irqenable_l0 = omap_dma_glbl_read(od, IRQENABLE_L0); + od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1); + od->context.ocp_sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); + od->context.gcr = omap_dma_glbl_read(od, GCR); +} + +static void omap_dma_context_restore(struct omap_dmadev *od) +{ + int i; + + omap_dma_glbl_write(od, GCR, od->context.gcr); + omap_dma_glbl_write(od, OCP_SYSCONFIG, od->context.ocp_sysconfig); + omap_dma_glbl_write(od, IRQENABLE_L0, od->context.irqenable_l0); + omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1); + + /* Clear IRQSTATUS_L0 as legacy DMA code is no longer doing it */ + if (od->plat->errata & DMA_ROMCODE_BUG) + omap_dma_glbl_write(od, IRQSTATUS_L0, 0); + + /* Clear dma channels */ + for (i = 0; i < od->lch_count; i++) + omap_dma_clear_lch(od, i); +} + +/* Currently only used for omap3 */ +static int omap_dma_context_notifier(struct notifier_block *nb, + unsigned long cmd, void *v) +{ + struct omap_dmadev *od; + + od = container_of(nb, struct omap_dmadev, nb); + + switch (cmd) { + case CPU_CLUSTER_PM_ENTER: + omap_dma_context_save(od); + break; + case CPU_CLUSTER_PM_ENTER_FAILED: + case CPU_CLUSTER_PM_EXIT: + omap_dma_context_restore(od); + break; + } + + return NOTIFY_OK; +} + #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) +/* + * No flags currently set for default configuration as omap1 is still + * using platform data. + */ +static const struct omap_dma_config default_cfg; + static int omap_dma_probe(struct platform_device *pdev) { + const struct omap_dma_config *conf; struct omap_dmadev *od; struct resource *res; int rc, i, irq; - u32 lch_count; od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); if (!od) @@ -1473,6 +1562,12 @@ static int omap_dma_probe(struct platform_device *pdev) if (IS_ERR(od->base)) return PTR_ERR(od->base); + conf = of_device_get_match_data(&pdev->dev); + if (conf) + od->cfg = conf; + else + od->cfg = &default_cfg; + od->plat = omap_get_plat_info(); if (!od->plat) return -EPROBE_DEFER; @@ -1522,18 +1617,19 @@ static int omap_dma_probe(struct platform_device *pdev) /* Number of available logical channels */ if (!pdev->dev.of_node) { - lch_count = od->plat->dma_attr->lch_count; - if (unlikely(!lch_count)) - lch_count = OMAP_SDMA_CHANNELS; + od->lch_count = od->plat->dma_attr->lch_count; + if (unlikely(!od->lch_count)) + od->lch_count = OMAP_SDMA_CHANNELS; } else if (of_property_read_u32(pdev->dev.of_node, "dma-channels", - &lch_count)) { + &od->lch_count)) { dev_info(&pdev->dev, "Missing dma-channels property, using %u.\n", OMAP_SDMA_CHANNELS); - lch_count = OMAP_SDMA_CHANNELS; + od->lch_count = OMAP_SDMA_CHANNELS; } - od->lch_map = devm_kcalloc(&pdev->dev, lch_count, sizeof(*od->lch_map), + od->lch_map = devm_kcalloc(&pdev->dev, od->lch_count, + sizeof(*od->lch_map), GFP_KERNEL); if (!od->lch_map) return -ENOMEM; @@ -1605,6 +1701,11 @@ static int omap_dma_probe(struct platform_device *pdev) } } + if (od->cfg->may_lose_context) { + od->nb.notifier_call = omap_dma_context_notifier; + cpu_pm_register_notifier(&od->nb); + } + dev_info(&pdev->dev, "OMAP DMA engine driver%s\n", od->ll123_supported ? " (LinkedList1/2/3 supported)" : ""); @@ -1616,6 +1717,9 @@ static int omap_dma_remove(struct platform_device *pdev) struct omap_dmadev *od = platform_get_drvdata(pdev); int irq; + if (od->cfg->may_lose_context) + cpu_pm_unregister_notifier(&od->nb); + if (pdev->dev.of_node) of_dma_controller_free(pdev->dev.of_node); @@ -1637,12 +1741,34 @@ static int omap_dma_remove(struct platform_device *pdev) return 0; } +static const struct omap_dma_config omap2420_data = { + .lch_end = CCFN, +}; + +static const struct omap_dma_config omap2430_data = { + .lch_end = CCFN, +}; + +static const struct omap_dma_config omap3430_data = { + .lch_end = CCFN, + .may_lose_context = true, +}; + +static const struct omap_dma_config omap3630_data = { + .lch_end = CCDN, + .may_lose_context = true, +}; + +static const struct omap_dma_config omap4_data = { + .lch_end = CCDN, +}; + static const struct of_device_id omap_dma_match[] = { - { .compatible = "ti,omap2420-sdma", }, - { .compatible = "ti,omap2430-sdma", }, - { .compatible = "ti,omap3430-sdma", }, - { .compatible = "ti,omap3630-sdma", }, - { .compatible = "ti,omap4430-sdma", }, + { .compatible = "ti,omap2420-sdma", .data = &omap2420_data, }, + { .compatible = "ti,omap2430-sdma", .data = &omap2430_data, }, + { .compatible = "ti,omap3430-sdma", .data = &omap3430_data, }, + { .compatible = "ti,omap3630-sdma", .data = &omap3630_data, }, + { .compatible = "ti,omap4430-sdma", .data = &omap4_data, }, {}, }; MODULE_DEVICE_TABLE(of, omap_dma_match); diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h index ee0de8443274..5c5c93ad6b50 100644 --- a/include/linux/omap-dma.h +++ b/include/linux/omap-dma.h @@ -327,8 +327,6 @@ extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); extern int omap_get_dma_active_status(int lch); extern int omap_dma_running(void); -void omap_dma_global_context_save(void); -void omap_dma_global_context_restore(void); #if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP) #include -- cgit