From d14bc28af34fb8b599c1cc4ce24a2833e60ade8f Mon Sep 17 00:00:00 2001 From: Shashank Babu Chinta Venkata Date: Wed, 11 Sep 2024 20:56:29 +0530 Subject: PCI: qcom: Add RX lane margining settings for 16.0 GT/s MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.org Tested-by: Johan Hovold Signed-off-by: Shashank Babu Chinta Venkata [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński Reviewed-by: Johan Hovold Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.h') diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h index 536387e02e29..7d88d29e4766 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.h +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h @@ -9,5 +9,6 @@ struct dw_pcie; void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci); +void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci); #endif -- cgit